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Metallic carbon nanotubes (m-CNs) cause malfunction by shorting the source and drain terminals in carbon nanotube transistors. To achieve high-yield with robust read and write operations, a new nine carbon nanotube MOSFET (9-CN-MOSFET) static random-access memory (SRAM) cell that can tolerate the removal of m-CNs is proposed in this paper. A functional yield model considering the spatial correlations of carbon nanotubes in channel arrays of CN-MOSFETs is developed. The yield of the m-CN-removal-tolerant 9-CN-MOSFET SRAM array is increased by 21309x as compared to a design that does not consider process imperfections in carbon-based electronics. Due to the increased strength of read and write ports, the read delay and worst-case write delay of the m-CN-removal-tolerant 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit that does not consider process imperfections in a 16-nm CN-MOSFET technology.

Metallic carbon nanotubes (m-CNs) cause malfunction by shorting the source and drain terminals in carbon nanotube transistors. To achieve high-yield with robust read and write operations, a new nine carbon nanotube MOSFET (9-CN-MOSFET) static random-access memory (SRAM) cell that can tolerate the removal of m-CNs is proposed in this paper. A functional yield model considering the spatial correlations of carbon nanotubes in channel arrays of CN-MOSFETs is developed. The yield of the m-CN-removal-tolerant 9-CN-MOSFET SRAM array is increased by 21309x as compared to a design that does not consider process imperfections in carbon-based electronics. Due to the increased strength of read and write ports, the read delay and worst-case write delay of the m-CN-removal-tolerant 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit that does not consider process imperfections in a 16-nm CN-MOSFET technology.

Metallic carbon nanotubes (m-CNs) cause malfunction by shorting the source and drain terminals in carbon nanotube transistors. To achieve high-yield with robust read and write operations, a new nine carbon nanotube MOSFET (9-CN-MOSFET) static random-access memory (SRAM) cell that can tolerate the removal of m-CNs is proposed in this paper. A functional yield model considering the spatial correlations of carbon nanotubes in channel arrays of CN-MOSFETs is developed. The yield of the m-CN-removal-tolerant 9-CN-MOSFET SRAM array is increased by 21309x as compared to a design that does not consider process imperfections in carbon-based electronics. Due to the increased strength of read and write ports, the read delay and worst-case write delay of the m-CN-removal-tolerant 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit that does not consider process imperfections in a 16-nm CN-MOSFET technology.