1. Buffer-aware Worst Case Timing Analysis of Wormhole Network On Chip
- Author
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Mifdaoui, Ahlem and Ayed, Hamdi
- Subjects
Computer Science - Networking and Internet Architecture ,Networking and Internet Architecture (cs.NI) ,Performance (cs.PF) ,FOS: Computer and information sciences ,Computer Science - Performance ,Computer Science - Distributed, Parallel, and Cluster Computing ,Distributed, Parallel, and Cluster Computing (cs.DC) - Abstract
A buffer-aware worst-case timing analysis of wormhole NoC is proposed in this paper to integrate the impact of buffer size on the different dependencies relationship between flows, i.e. direct and indirect blocking flows, and consequently the timing performance. First, more accurate definitions of direct and indirect blocking flows sets have been introduced to take into account the buffer size impact. Then, the modeling and worst-case timing analysis of wormhole NoC have been detailed, based on Network Calculus formalism and the newly defined blocking flows sets. This introduced approach has been illustrated in the case of a realistic NoC case study to show the trade off between latency and buffer size. The comparative analysis of our proposed Buffer-aware timing analysis with conventional approaches is conducted and noticeable enhancements in terms of maximum latency have been proved., Comment: ISAE Technical report done during the master Thesis of Hamdi Ayed at ISAE at 2010
- Published
- 2016
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