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Quality assurance in electronic components and systems requires effective test strategies to be applied to ICs of increasing complexity and size. The traditional voltage techniques based on logic observation of the outputs have been found insufficient to guaranty the low defect escape requirements of growing sectors of IC users. This fact has motivated the search for complementary testing techniques which try to detect defects escaping logic testing. This paper attempts to explore the state of the art and the perspective of the test based on the observation of the quiescent current consumption of the IC, generally known as I DDQ testing. After introducing the basic principle of the technique and the components of the quiescent current in CMOS technologies, the physical defects which cause an increase of the I DDQ are presented. The state of the art of the detection of circuits with sensor(s) located on-chip (BICS) and off-chip is explored. A literature review of the circuits to sense the quiescent current permits their classification according to their function and structure. The different techniques to generate the input vectors to force the increase in quiescent current consumption are presented and, as an example, an ATPG to detect bridging faults is presented in detail. Finally the future trends of I DDQ testing are discussed taking into account the implications of scaling in CMOS. As the power supply voltage is reduced to maintain the electric fields in the MOS transistors and the global power consumption, the threshold voltages of the devices need to be lowered to maintain or increase the speed of the logic. As a consequence, the quiescent current consumption, I DDQ , increases exponentially. This fact decreases the discriminability of nondefective in front of defective quiescent currents. On the other hand, techniques to reduce the leakage currents are becoming available thanks to an active research effort directed mainly to decrease the quiescent power consumption in submicron ICs.