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Memory cells comprising a Phase Change Material (PCM) are the building blocks of fast and non-volatile memory devices called Phase Change Random Access Memory (PCRAM) [1-3]. The working principle of this memory involves data retention in the form of a phase (amorphous or crystalline) and the set and reset can be done by Joule heating to induce an amorphous-to-crystalline or crystalline-to-amorphous transition respectively. Some chalcogenide materials experience this thermally driven phase change, GeSbTe (GST) being one of those alloys extensively studied. GST has also been adopted for the fabrication of the 1st generation X-point memory [4] and might be adopted in a 2nd generation X-point memory of a four-layer PCM structure [5]. However, this 2D scaling or stacking of PCRAM is limited by cost and therefore the development of 3D architectures is envisaged for decreasing the cost/bit [6]. A key requirement for the fabrication of this 3D architecture is the conformal deposition and etch-back of GST. Dry plasma etching might be limited to anisotropic recess while isotropic lateral recess is needed. Therefore, wet isotropic etching might be the process of choice. A few chemical solutions have been proposed in previous studies. Cheng et al. showed that GST could be etched in HNO3 but with a very high etch rate and with an unwanted surface composition change due to different oxidation and dissolution rates of the metalloids [7]. Wang et al. demonstrated that basic wet etching solutions led to a slower etch rate and a much smoother surface compared to acidic wet etching solutions [8]. Deng et al. showed a switch in the etch rate order between crystalline and amorphous GST depending on the H2O2 concentration in TMAH [9]. In this work, we present a controllable partial recess solution that leaves the GST surface smooth after recess. Wet recess of amorphous and crystalline blanket films, as well as patterned samples, was initially explored using the commodity chemistries Ammonium Peroxide Mixture (APM) and (Hydrochloric Peroxide Mixture) HPM. The etching of GST in HPM as a function of the H2O2 concentration was monitored by ICPMS and showed a well-controlled etch rate. However, some shortcomings of these H2O2-containing solutions, like roughness and selectivity, lead to a change of oxidizing agent from H2O2 to O3. In the O3-containing solutions, the selectivity towards Al2O3, SiO2, and TiN could be secured. The impact of the dissolved O3 concentration on surface roughness and etch rate as well as the uniformity of this wet etching process were assessed on a single wafer tool. Finally, the bulk and surface GST composition and oxidation post-recess were verified through XPS and ERD. REFERENCES: [1] D. Loke et al., “Breaking the Speed Limits of Phase-Change Memory.” Science, 2012, 336, 6088, 1566. [2] K. Ding et al., “Recipe for ultrafast and persistent phase-change memory materials.” NPG Asia Mater 12, 63, 2020. [3] F. Rao et al., “Reducing the stochasticity of crystal nucleation to enable sub-nanosecond memory writing.” Science, 2017, 358, 6369, 1423. [4] [internet] https://www.techinsights.com/blog/intel-3d-xpoint-memory-die-removed-intel-optanetm-pcm-phase-change-memory [5] [internet] https://www.techinsights.com/blog/memory/intels-2nd-generation-xpoint-memory [6] [internet] https://www.imec-int.com/en/imec-magazine/imec-magazine-october-2017/in-pursuit-of-high-density-storage-class-memory [7] H.Y. Cheng et al., “Wet-Etching Characteristics of Ge2Sb2Te5 Thin Films for Phase-Change Memory.” IEEE Trans. Magn., 41, 2, 2005. [8] L. Wang et al., “Basic Wet-Etching Solutions for Ge2Sb2Te5 Phase Change Material.” J. Electrochem. Soc., 157, H470, 2010. [9] C. Deng et al., “XPS study on the selective wet etching mechanism of GeSbTe phase change thin films with TMAH.” Proc. of SPIE, 8782, 87820N, 2012.

The steam oxidation of SiGe shows a transition from Si-like to Ge-like oxidation behavior depending on Ge concentration and oxidation temperature. Ge-like oxidation is described by the generation of oxygen vacancies (VO) at the interface between the oxide and SiGe virtual substrate. [1] Due to the different oxidation behavior, the presence of a Ge-oxide-free interfacial layer (IL) can suppress SiGe oxidation. [2] Here we show how a passivating interfacial layer can be grown using low-pressure oxidation and highlight the importance of SiGe surface preparation prior to low-pressure oxidation.

This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si x )Ge1- x O y , which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced ${D}_{{\text {IT}}}$ , and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum ${V}_{{\text {OV}}}$ of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm- ${L}_{g}$ n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.

Like supervias in the back end of line, and deep contact holes with an aspect ratio higher than sixty in 3D-NAND memory, higher aspect ratio patterning is one of the important issue in advanced semiconductor manufacturing. As with the difficulty of patterning, the technique of cleaning the nanostructure so that it does not affect the next process is also considered important. In semiconductor cleaning, chemicals such as HF and NH4OH that include reactant ions are used for cleaning the semiconductor surface. Ions in bulk aqueous solutions were shown either as structure making or breaking effects in Marcus’s study (Chem. Rev., 2009). The classification of ions as structure making or breaking was confirmed using 1 M solutions in nanotrenches (Vereecke, Micro. Eng., 2021). This shows there is an ion effect, and it can change properties between solution and material surface. The addition of structure breaking ions in HF solutions was used to decrease the etch rate of oxide between fins (Vereecke, Micro. Eng., 2022). Going further from Marcus’s study, we focused on pH and ion concentration in the addition of structure making ions. In the nanostructure, it was considered necessary to study because the surface properties may vary depending on the degree of structuring and the influence of the zeta potential depending on the concentration and pH of the ions. In this work, we used an in-situ ATR-FTIR (Attenuated Total Reflection – Fourier Transformed Infra-Red) spectroscopy technique (Nicolet iS50 AEM, Thermo Fisher Scientific, USA) to characterize the wetting of nanostructures embedded in a silica matrix by UPW (Ultra-Pure Water) and electrolyte solutions, and a streaming zeta potential analyzer (SURPASS3, Anton Paar, Austria) to characterize the surface potential of flat surfaces of the same material. Wetting in the nanostructures was characterized by an analysis of the ratio of the OH stretching peak to OH bending peak (Vrancken, Langmuir, 2016). Also, dissolution of CO2 in the wetted nanostructures was monitored to compare the solubility and diffusivity in the nano-confined solutions with that in bulk solutions. In this experiment, we used dense arrays of silicon nanoholes in a PEALD SiO2 matrix (depth of about 300 nm, diameter of about 20 nm, and pitch 90 nm) that were fabricated on Si wafers using arrays of nanostructures, as described in Vereecke (2021). Crystal drying, wetting with a solution, and applying CO2 were performed in this order. HI, HBr, HCl were used for chemicals and pH 1, 2, 3, 4 was used for pH. Monitoring of the OH stretching to bending ratio showed little improvement in wetting as a function of pH between 1 to 4 as compared to UPW. Also, little difference was observed when changing the acid from HCl to HBr and HI, with anions of higher structure breaking properties according to Marcus (Chem. Rev., 2009). A higher CO2 solubility and a lower CO2 diffusivity were measured in the nanoconfined solutions as compared to bulk UPW, indicative of water structuring. A higher CO2 solubility at pHs 2-3 as opposed to pH 1 and 4 may originate from the proximity to the isoelectric point. Results will be complemented with tests performed at the isoelectric point and pH 0, with 1 M solutions where structure breaking properties of the used anions are expected to be stronger and wetting might be improved.

Water structuring has been proposed to occur in water confined in nanochannels and nanoholes based on shifts of the OH stretching peak in Attenuated Total Reflection – Fourier Transformed Infra-Red (ATR-FTIR) measurements (Vereecke, Micro. Eng., 2021 and 2022). Nanoconfined water was characterized by the presence of H-bonds with a stronger vibration frequency compared to ice. Using CO2 as a probe molecule in ATR-FTIR measurements on nanoholes, it was also shown that nanoconfined water was characterized by a slower diffusivity and a lower permittivity compared to bulk water (Vereecke, Micro. Eng., 2021), in agreement with previous studies performed using different techniques (Mawatari, Anal. Chem., 2014; Morikawa, Anal. Chem., 2015). Also, the decreased rate of a model surface reaction performed in nanotrenches of decreasing width correlated well with water structuring characterized by IR spectroscopy (Vereecke, Solid State Phenom., 2018). In the present study, X-Ray diffraction (XRD) measurements were used to further characterize the structuring of water confined in nanoholes. XRD measurements were performed on a X’pert Pro from Malvern Panalytical equipped with a PixCel detector. Measurements were performed on a parametric space defined by an incident XR angle w varying from 3 to 23°, and a spectra angle 2q varying from 12 to 42°. Measurements of 101 spectra with Dw = 0.2 took 2 days 7 hours. ATR-FTIR measurements were performed in a flow cell on crystals made from wafers as described in Vereecke (Micro. Eng., 2021). The cell was equipped with a bubbler filled with water to control the relative humidity (RH) of the N2 flow in the cell. Samples consisted in nanoholes in an oxide matrix with a diameter of about 20 nm and a depth of about 300 nm, manufactured on Si wafers as described in Vereecke (Micro. Eng., 2021). The last step in making the nanoholes structure consisted in a 30 min bake at 400 °C to remove any tetra-methyl ammonium hydroxide (TMAH) residue present in the holes from etching. The contact angle (CA) of pristine nanoholes was less than 5°. It was increased by silanization treatments. One treatment consisted in the classical HMDS priming photoresist pre-treatment, which gives a CA of about 70° on a flat Si substrate, while the second consisted in the SMT treatment developed by SCREEN, which gives a CA of about 80° on a flat Si substrate. These treatments were performed immediately after drying the sample to prevent any condensation before silanization. Long XRD measurements were made possible by the anomalous capillary condensation occurring in the 20 nm nanoholes. In turn, condensation was evidenced by ATR-FTIR measurements by monitoring the OH stretching peak. Condensation occurred in nanoholes submitted to a 200 °C bake in about 30 min when submitted to the clean-room air with a RH of about 40%. On the other hand, no condensation was observed in nanoholes under a N2 flow with a RH of about 30%, indicating that condensation was not an artefact, caused for example by the presence of impurities in the nanoholes, but was truly the result of capillary condensation. XRD measurements showed the presence of a small peak varying as a function of w, from about 2q = 28° at w = 15° to 2q = 33° at w = 18°, which was not present in the Si and oxide references. This peak was close to the 27° peak of ice-VII that has been identified by Raman spectroscopy measurements in water condensed in the nanomeniscus of nanoparticles (Shin, Nature Commun., 2019). The peak was not changed by ageing of the sample from 2 days to 2 months. It was also observed in samples that had been submitted to silanization treatments, bringing the CA on flat substrates from about 5° for the pristine sample, to 70° and 80° for the sample submitted to the HMDS priming and the SMT clean, respectively. This peak was evidence for structuring of water confined in nanoholes. Shifting of the peak as a function of w indicated that water structuring in nanoholes was comparable to a monocrystalline structure. However, the structure of nanoconfined water differed from that of ice-VII. Indeed, the presence of a broad peak at about 22°, which was not observed in the oxide reference, indicated the simultaneous presence of bulk H2O in the nanoholes. These observations added to our understanding of structured water in nanoholes that had been proposed previously based on ATR-FTIR measurements.

This paper shows the importance of oxygen control at the SiGe fin surface and within the gate stack. Optimized SiN liners are required to protect SiGe fins from oxidation during a flowable CVD (FCVD) densification anneal. Suppression of oxygen diffusion or scavenging from GeO via metal electrode is essential to achieve a low-D IT SiGe gate stack. By replacing HfO 2 with other dielectrics offering lower oxygen diffusivity, impact of metal electrode deposition process as well as the HfO 2 nitridation is corroborated to be related to the oxygen diffusivity. Finally, when using an embedded B-doped Si 0.4 Ge 0.6 S/D, higher channel strain in Si 0. 7 Ge 0.3 than in Si p-fins is obtained as predicted by TCAD.

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.

A selective wet etching process for fabricating SiGe and Ge nanowires for gate all around transistors is introduced in this paper. Two formulated proprietary chemical mixtures with highly selective etching properties (Si vs. SiGe and SiGe vs. Ge) can effectively dissolve the sacrificial layers with minimal damage to the interstitial nanowire materials. The Auger Electron Spectroscopy (AES) surface characterization indicates that no chemical contamination is left after the wet etching process.

For horizontally stacked nanowires or-sheets to compete with finFET, the development of a robust inner spacer module is essential. These inner spacers are required to reduce the parasitic capacitance due to the overlap between the source/drain and gate regions. Here we propose an inner spacer integration scheme for Si gate-all-around (GAA) taking advantage of the selective oxidation and oxide removal of SiGe versus Si. Compared to thermal oxide, we found a very high SiGe-oxide etch rate in aqueous HF solutions. When using an NH3/NF3remote plasma, a reduction in etch rate was found for SiGe-oxide versus thermal oxide. We show Si0.75Ge0.25-oxide meets inner spacer requirements for leakage current and electrical breakdown field and finally demonstrate the proposed inner spacer integration scheme using a fin-shaped SiGe/Si multilayer topological-test-structure.

Gate All-Around (GAA) is considered a key design feature for future CMOS technology. SiGe vs. Si selective etch is required for Si nanowire formation in GAA. It is confirmed the selective SiGe removal with commodity chemical (mixtures of hydrofluoric acid (HF), hydrogen peroxide (H2O2) and acetic acid (CH3COOH, HAc)), however the thick oxidized layer on Si NW was observed after commodity chemical process, which is indicated the significant Si NW loss. On the other hand, the formulated mixture ACT® SG-101, which is focusing on SiGe oxidizer, chemical pH, solvent polarity & corrosion inhibitor for chemical concept, was performed higher selectivity and lower Si loss than commodity chemical. The formulated mixture has also been used to form an inner spacer for cavity etch scheme and confirmed uniform cavity etch and inner spacer filling on topological test structure.

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions ( $L_{G}= 40$ nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub-20 nA/ $\mu \text{m}~I_{\mathrm{\scriptscriptstyle off}}$ at $V_{\mathrm {{\text {DD}}}}= -0.5$ V and $L_{G}= 40$ nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any $L_{G}= 40$ -nm Ge pMOS channel device.

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (NIT) down to 2 1011 cm-2 have been demonstrated. [1-3] A clear correlation was established between Ge-content in the SiGe-oxide and NIT. Unfortunately no process information has been provided on how the Ge-oxide-free interlayers were obtained. In a separate study the impact of HF, HCl and SC1 cleaning solution on the SiGe surface and oxide composition was reported. [4] A comparison of SiGe Gate-All-Around (GAA) and FinFET devices using a Si-cap-free SiGe 25% passivation scheme in a replacement metal gate (RMG) integration indicate the device performance is improved by a TMAH (aq) treatment prior to SiGe interlayer formation and high-k deposition. [5] Here the formation of a SiGe wet chemical oxide will be presented. The impact of dummy gate processing on the interlayer composition is reported. Also the impact of a TMAH (aq) treatment prior to chemical oxide formation has been analyzed and will be reported. Blanket strained SiGe 25% and 45% were grown by epitaxy. The SiGe-substrate and -oxide composition were measured by angle-resolved XPS using the Si2p and Ge3d peaks. The Ge3d peak is fitted with three different compounds: elemental Ge, GeO2 and Ge-suboxide. The angle dependence lets us estimate the distribution of the different components with respect to the sample top surface. An concentration increase with increasing angle (relative to the surface normal) indicates the compound is located closer to the sample surface. And reversely a concentration increase with increasing angle indicates the compound is located deeper into the sample. A native oxide was grown on SiGe 25 and 45% by exposing the wafers to the cleanroom air for approx. 1 week. The native oxide was found to be stoichiometric or nearly stoichiometric with a uniform Ge content throughout the oxide for SiGe 25 and 45% respectively. A wet chemical oxide was grown using an ‘imec clean’ [6] having a final O3/HCl (aq) rinse. The wet chemical oxide is Ge-poor compared to the SiGe substrate. No or only a small variation in Ge content of the SiGe-oxide is seen with ARXPS. However the fraction Ge-suboxide decreases with increasing angle, indicating the Ge-suboxide are located deeper within the sample, so closer to the SiGe-oxide/SiGe-substrate interface. The Ge-content of the SiGe-substrate after wet chemical oxidation shows a weak incident-angle-dependence, indicative a limited Ge enrichment of the SiGe substrate towards the SiGe-oxide/-substrate interface. The low Ge content of the SiGe-oxide is attributed to the water solubility of GeO2. The increase in Ge-content towards the SiGe-oxide/-substrate can be (at least partially) attributed to the poor water solubility of Ge-suboxide. The small increase in Ge content of the SiGe substrate can be attributed to the thermodynamically preferred oxidation of Si over Ge. The combined impact of dummy gate deposition, spike anneal and dummy gate removal prior to SiGe interlayer formation was investigated by AR-XPS and SIMS. The temperature used during spike anneal was found to have a significant impact on the Ge-content of the SiGe-oxide formed during an O3-last imec clean. The results will be reported in detail at the conference. The impact of TMAH (aq) on the chemical oxide composition and surface roughness will also be reported. TMAH (aq) was found to improve SiGe device performance. [5] Also the interaction with the subsequent HfO2 deposition will be reported. In summary SiGe is found to behave as a non-linear combination of Si and Ge. In HF-free aqueous solutions, the SiGe oxide composition is a combination of (1) thermodynamically preferred oxidation of Si versus Ge; (2) poor water-solubility of SiO2 and/or its low solubilization rate; and (3) fast dissolution of GeO2 but slow dissolution of Ge-suboxides. [1] CH Lee et al. VLSI 2016. [2] S. Siddiqui et al. presented MRS Spring Meeting 2016. [3] CH Lee et al. IEDM 2016. [4] S.L. Heslop et al. ECS Trans 69 (2015) 287. [5] H. Mertens et al VLSI 2015. [6] M. Meuris et al. Solid State Phenom, July 1995, p. 109. Figure 1

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

We demonstrate multiple ways to reduce the D IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D IT reduction, while nitridation of the HfO 2 dramatically reduces D IT by negating an ALD TiN-induced D IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si 0 7 Ge 0 3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.

We have demonstrated Ge nFinFETs with a record high $\text{G}_{\text{mSA}\Gamma}/\text{SS}_{\text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO 2 dummy gate oxide (DGO) deposition and removal processes have been identified as knobs to improve electron mobility and PBTI reliability even with a nominally identical Si-passivated Ge gate stack. Surface oxidation of Ge channel during the DGO deposition is considered to impact the final gate stack. By suppressing the Ge channel surface oxidation, increasing mobility with decreasing fin width is obtained, whereas PBTI reliability, $\text{D}_{\text{IT}}$ of scaled fin as well as high-field mobility are improved by extending the DGO in-situ clean process, resulting in the record $\text{Gm}_{\text{SAT}}/\text{SS}_{\text{SAT}}$ of 5.4 at 73 nm Lg.

Ultrapure water contains dilute hydrogen peroxide as an impurity. In order to clarify an impact of the dilute hydrogen peroxide on cleaning processes, a SiGe epitaxial layer was deposited on a Si(100) wafer which surface was treated by HF last process with hydrogen peroxide contained UPW or hydrogen peroxide removed UPW. The defect in the SiGe epitaxial layer was reduced when the hydrogen peroxide removed UPW was used.

With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.

This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, I on =500μA/μm at I off =100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si 0.3 Ge 0.7 SRB.

Introduction The usage of germanium has recently been considered for the MOSFET channel in order to improve the performance of the integrated semiconductor devices. Since Ge is oxidized easily and dissolves in to the wet solution, much attention is required for wet cleaning process with minimal dissolution of Ge. The present study covers the mechanism of Ge dissolution in sulfuric acid based solution in view of different application as the selective NiPt-etch during germanidation and the IIPR strip from Ge. Experiments 80nm Ge layers were epitaxially grown on 300mm Si wafers. These wafers were cut into coupons for following tests to determine the Ge loss in sulfuric acid based solutions. All tests were performed in a beaker at 30 degrees C and the amount of each solution was 50ml. (1) Dissolution phenomenon Coupons were immersed in the sulfuric acid based solutions, 30 to 98 wt% sulfuric acid with and without 5g/L of an oxidizer. The oxidizer used in the study is peroxosulfuric acid generated by Electrolyzing Sulfuric Acid, and is referred hereinafter to ESA. The dissolution of the Ge in the sulfuric acid solution was assessed by ICP-MS (Inductively Coupled Plasma-Mass Spectrometry), and it allowed us to calculate the dissolved volume and dissolution rate. (2) Dissolution mechanism In order to study the dissolution mechanism in the sulfuric acid based solutions, the surface of the coupon was examined with XPS (X-ray Photoelectron Spectroscopy) before and after immersion to 30wt% sulfuric acid solution and 2wt% hydrogen peroxide solution. The solutions were subjected to ICP-MS after immersion and the results were compared with the XPS data. Results and discussion (1) Dissolution phenomenon Figure 1 shows the dissolution rate of Ge after immersing the different coupons in the sulfuric acid based solutions, 30 to 98 wt% sulfuric acid with and without 5g/L of an oxidizer. When no oxidizer is added, the Ge dissolution rate is less than 1nm/min regardless of sulfuric acid concentration. However, it can be observed that Ge dissolved in an inverse proportion to the sulfuric acid concentration when the oxidizer is existed in the solution. (2) Dissolution mechanism Results of XPS analysis conducted on the original surface before immersion as shown in Figure 2. Peaks for Ge, GeO and GeO2 are apparent. When the coupons were immersed in the sulfuric acid, the XPS determinate that no GeO2 is present and only Ge and GeO are remained. When immersed in the hydrogen peroxide solution, both Ge and GeO peaks are detected but GeO peak is much weaker than that with sulfuric acid. No GeO2 is present in either condition. Additionally, a significant increase in dissolution is observed when the Ge coupon was immersed in hydrogen peroxide solution. These results indicate that GeO2dissolves readily in all solutions tested, and that GeO does not serve as a strong passive film during dissolution, and that active dissolution of Ge requires both water and oxidizer. Proposed dissolution reaction is: GeO2 + H2O → HGeO3 -+ H+ GeO + 2H2O → HGeO3 -+ 3H+ + 2e- Ge + H2O → GeO + 2H++ 2e- Considering the peaks of the original surface and the effect of UPW and sulfuric acid above mentioned, the foremost surface is GeO2as shown in Figure 3. Conclusion Conclusions drawn from the present study are as follows; 1) Dissolution of Ge is inversely proportional to sulfuric acid concentration only when an oxidizer is present in its solution. 2) The surface of Ge consists of three layers, i.e. GeO2, GeO and and Ge with the foremost layer being GeO2. 3) Only GeO2 dissolves in solutions without oxidizer, but Ge readily dissolves only when it is present in the solution. The ultimate goal of the present study is to enable either the selective etch of the both NiPt-etch during germanidation or strip IIPR from Ge without germanide or Ge dissolution. When Ge is treated with sulfuric acid including an oxidizer, as shown Figure 1, the higher sulfuric acid concentration is, the less Ge dissolution rate is. This result indicates that it is important to keep sulfuric acid concentration as high as possible when sulfuric acid with oxidizer is applied for Ge wet cleaning process. SPM is difficult to apply for Ge wet cleaning process because it is a mixture of sulfuric acid and 30wt.% hydrogen peroxide in order to generate oxidizer. Since the water from 30wt.% hydrogen peroxide results the sulfuric acid concentration of SPM lower, SPM dissolves Ge easily. Figure 1

Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (L g =40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (L g =40nm) with DIBL of 30mV/V and sub-threshold slope (SS sat ) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

This paper shows high-pressure anneal (HPA) as a performance booster for Si-passivated strained Ge (sGe) p-channel FinFET and gate-all-around (GAA) devices. Improved interface quality and hole mobility (∼600 cm2/Vs) are obtained on FinFET after HPA at 450°C. While V th is tuned by ∼400 mV using TiAl work function metal (WFM), HPA-induced increases in J g and NBTI are suppressed by barrier layer engineering under the TiAl. Finally, the optimized HPA is also shown to improve the electrostatics and overall performance of GAA devices, reaching SS lin of 65 mV/dec at L g =60 nm and a Q factor of 15 with low I off of ∼3×10−9 A/μm.

Novel scaling approaches such as sGe channels on strain relaxed SiGe buffers, source/drain (S/D) stressors for FINFETs are usually grown using epitaxial process. Prior to the epitaxial growth, the starting surface should be free from oxygen and organic impurities. If not, these impurities would act as nucleating centres for defect formation resulting in defective epi growth. Conventionally, the wafers are HF dipped and then subjected to in-situ hydrogen bake at a temperature of 800°C in order to remove the above said impurities present on the wafer surface [1]. However, subjecting the strain relaxed SiGe to such high temperature baking would lead to roughening/islanding and subjecting the fins to high temperature baking might result in severe surface reflow [2]. As a result, the device performance would be adversely affected.

Epitaxial growth requires a clean starting surface for the growth of a high-quality crystalline layer. For epitaxy on Si, an HF-last wet clean followed by an in-situ high-temperature hydrogen bake is the reference pre-epi clean sequence to obtain an oxygen-free surface [1, 2]. The temperature required to remove all residual oxygen also makes the surface atoms mobile, resulting in reflow. The high temperatures used during the H2-bake can also result in intolerable doping profile changes. A lower temperature pre-epi clean sequence is required to avoid this reflow, especially when moving away from Si. In addition the high temperatures needed during a H2-bake would result in the relaxation of high mobility channels, e.g. strained Si1-xGex or III-V materials [3]. Several low temperatures pre-epi cleaning solutions have been proposed in the past, e.g. GeH4-assisted H2-bake [4] or more recently, a GeH4-assisted HCl clean [5]. In this study we looked at the interaction between HF-last wet clean and the in-situ GeH4-assisted HCl clean prior to Si0.8Ge0.2-on-Si epitaxy.

Inline light scattering measurements are frequently used to determine wafer quality and cleanliness. In this paper we will show how this technique can be extended to determine the crystalline quality after hetero-epitaxy. Misfits on the surface of the epitaxially grown layer cause increased surface light scattering. The Si0.8Ge0.2-on-Si epitaxial quality has been evaluated by surface light scattering and correlated with the controlled variation of the interfacial oxygen between the Si substrate and epitaxially grown Si0.8Ge0.2. SiGe-on-Si hetero-epitaxy is used for strain engineering in transistors. SiGe, Ge and III-V materials are also under consideration as transistor channel in future technology nodes. [1] With the current need for low thermal budget processing in combination with the move to non-planar device structures like FINFETs, oxygen contamination at the Si substrate - epitaxial SiGe interface which is known to degrade the SiGe crystalline quality, is receiving some renewed interest. [2] Dislocations formed during SiGe epitaxy can extend to the surface of the epitaxial layer where they will be present as surface steps. Surface imperfections can be detected by optical differential interference contrast (Nomarski) microscopy. Several other techniques are available and in use to inspect the strained epi layer e.g. HRXRD, TEM and lifetime measurements. In this paper, we will show how hetero-epitaxial-crystalline quality can be evaluated using surface light scattering. Surface imperfections can also be detected by scanning laser light scattering and quantified using a hazeline algorithm present on the KLA-Tencor Surfscan SP3. Previously, this algorithm has been demonstrated to quantify CMP scratches. [3] Figure 1a shows a 2D plot of the so-called haze component surface light scattering intensity of an epitaxial 80nm Si-cap/80nm Si0.8Ge0.2 bilayer grown on a 300mm Si substrate (ASM Epsilon 3200) measured by a KLA-Tencor Surfscan SP3. The epitaxial layer is grown on a Si substrate in a one-step process after a diluted HF last surface treatment followed by a 2 min H2 bake at different temperatures. Optimal and non-optimal bake conditions have been used to obtain a controlled variation of the remaining oxide on the Si substrate surface on top of which the epitaxial layer is grown. The light scattering plot clearly shows the presence of defects that follow the crystallographic directions of the Si substrate. The interfacial oxygen correlates well with SiGe epitaxial quality as quantified by the hazeline algorithm. (see Fig. 1b) In this paper we demonstrate the use of inline light scattering to quantify the epitaxial quality of Si0.8Ge0.2 grown on a Si substrate. Its advantages and its limitations will be explained. [1] M.L. Lee et al. Appl. Phys. Rev. 97 (2005) 011101 [2] V. Machkaoutsan, ECS Transactions 50, (2012) 339 [3] B. Pinto et al. Yield Management Solutions (Spring 2007) 28-32 Figure 1: (a) 2D plot of the surface light scattering intensity. The notch of the 300 mm wafer is facing the bottom of the picture; and (b) interfacial oxygen (open symbols) between the epitaxial SiGe and Si substrate and hazeline area (closed symbols) as a function of the H2 bake temperature.

The Gate-All-Around (GAA) architecture constructed of vertically stacked horizontal Silicon Nano-Wires (Si NWs) are a promising candidate to replace FinFET for device scaling at sub 5-nm technology nodes. In this paper, Si NWs’ release, which is the sacrificial film etching of SiGe 25% (Silicon0.75 Germanium0.25) selective to Si, will be presented. It is known that the boundary layer between Si and SiGe 25% in the multistack is very sharp, since Ge diffusion depth into Si is generally limited up to 1nm. However, the thermal annealing process is known to cause intermixing of SiGe/Si at the boundary layer with an intermixing depth ranging from 1 to 2 nm [1]. In other words, there is a possibility of Ge residue remaining at the Si NWs’ surface after the selective etch of the sacrificial SiGe 25% film using a formulated chemistry [2]. The presence of impurities on the Si NWs channel surface is expected to cause an increase in leakage current causing a degradation in device performance. Therefore, the motivation in this study is to investigate the Ge residue in Si NWs after SiGe:Si selective etching and means of removal them from the Si NWs’ surface. To investigate the surface clean, blanket wafers of 50-nm SiGe 25% on Si were prepared by epitaxial growth. The SiGe 25% layer was then removed using the formulated chemical. These wafers were analyzed by dynamic SIMS and confirmed the diffusion of Ge into Si, which indicates the need of a subsequent surface clean to remaining Ge. At first, various commodity chemicals like HF, HCl and HPM (a mixture of HCl/H2O2/H2O) followed by DIW rinse were evaluated; however, none of these reduced the level of diffused Ge. Similarly, there was no further Ge reduction even with additional process time with the formulated chemical. Finally, APM (a mixture of NH4OH/H2O2/H2O) followed by DIW rinse was investigated, and the Ge concentration on the Si surface was reduced. The H2O2 oxidized Ge to Ge (OH)2, which subsequently dissolved in H2O [3][4]. Furthermore, the H2O2 oxidized the Si surface to SiO2, which was etched by NH4OH. As a result, it is proposed that the intermixing layer of SiGe/Si of Si surface was etched with concomitant reduction of the Ge concentration on the Si surface [5]. The intermixing layer of SiGe/Si has a much lower Ge concentration than SiGe 25%. Therefore, the chemicals that are effective for Si etching should also be effective for removing the intermixing layer of SiGe/Si [6][7]. The result of etching the intermixing layer of SiGe/Si with these chemicals will be presented. In addition, the surface roughness compared to before post process was improved, which is also beneficial for enhancing device performance. Furthermore, the impact of the thermal budget during the annealing process on the removal performance of Ge residue and the difference of intermixing depth of SiGe/Si will be shown. Finally, the most efficient post cleaning for Si NWs will be proposed. In summary, the Ge residue remaining at the Si NWs channel surface, which could not be removed by the formulated chemistry, will be efficiently removed by etching this intermixing layer. It will be shown that an optimized clean after the Si NWs’ release can be effective in removing Ge residue from this Si channel surface. [1] H. Mertens et al., ECS Transactions, 77 (5) 19-30 (2017) [2] K. Komori et al., UCPSS.1662-9787, 282,107-112(2018) [3] K. Komori et al., ECS Transactions, 80(2) 141-146 (2017) [4] N. Cerniglia et al., J. Electrochem. Soc, 109(6) 508-125(1962) [5] G. K. Celler et al., Electrochemical and Solid-State Letters, 3 (1) 47-49 (2000) [6] J. Phys. Chem. C, 118, 4, 2044-2051(2014) [7] O. Tabata et al., Sensors and Actuators A, 34(1) 51-57(1992)

The CMOS devices with Ge, considered as one of new materials for the later 5-nm generations, has been investigated since Ge should be mandatory material to enhance the electron mobility as replacement for Si. In this paper, we will propose new two techniques for surface preparation and wet cleaning, one of two techniques is in terms of PRE (Particle Removal Efficiency) on Ge surface, and the other is Ge corrosion caused by the dissolved oxygen effect. High PRE without Ge loss was achieved for surface preparation by using O 3 /NH 4 OH mixture. And to add to it, excellent selective Ni removal along germanidation (NiGe generation) without Ge corrosion was realized by reducing dissolved oxygen in chemistry.

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×1010 cm−2eV−1 around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×108 cm−2 at V ov /CET=3.5 MV/cm). Insertion of a 3D-compatible thin ALD LaOx, MgOx and LaSiO layer at the interface between HfO2 and SiO2/Si/Ge improves PBTI reliability thanks to the interface dipole-induced band engineering. The high DIT of Si-passivated Ge nFET is dramatically reduced by ∼40x around midgap using a combination of the LaSiO insertion and a H2 high-pressure anneal (HPA). These key gate stack technologies realize further improvements in mobility (∼50% at peak) and PBTI reliability (V ov =0.32 V for 10 years) of Si-passivated Ge nFETs.

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for L G = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

The cumulative installed solar power generation has been rising exponentially over the past decade. This has lead to a concomitant rise in production capabilities, leading eventually to excess production capabilities and rapid price declines per unit. In order to compete with the standard electricity generation the cost of solar panel production and installation needs to decrease even further. At the same time the solar panel and cell makers need to be able to keep a healthy margin. A crucial element in this exercise is a close control on the Cost of Ownership (CoO) of a solar cell / panel fabrication site.

In order to minimize the considerable loss of Si material during the processing of a silicon photovoltaics (PV) substrate into a solar cell, the optimization of the saw damage (SD) removal is an important step. The PV cell process therefore requires a routine metrology solution suitable to probe the SD present in the substrate. Though cross-sectional Transmission Electron Microscopy is typically used for this purpose, this technique is not suited for in-line measurements. It is furthermore destructive, time-consuming and limited to very small sampling volumes. In this paper, we demonstrate the capabilities of the Photomodulated Optical Reflectance (PMOR) method for the in-line measurement of SD. PMOR is a laser-based pump-probe technique, wherein the probe laser measures the reflectance of the sample (DC reflectance) as well as the change in reflectance (AC reflectance) which the pump laser has induced by optically injecting excess carriers and heat. As PMOR is a local and nondestructive technique, it offers a very promising approach for the simultaneous characterization of roughness and SD. We demonstrate the versatility of this approach and the response of the DC and AC reflectances when studying wafers which have undergone successive etchings to remove the SD sequentially (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Exposure of TSVs from the backside in 3D-SIC is a multistep process [1-. Two steps in this process flow (thinning module) are potentially a high risk for particle contamination: wafer edge trimming and wafer thinning by grinding.

Thermal atomic layer deposition (ALD) of Al2O3 provides an adequate level of surface passivation for both p-type and n-type Si solar cells. To obtain the most qualitative and uniform surface passivation advanced cleaning development is required. The studied pre-deposition treatments include an HF (Si-H) or oxidizing (Si-OH) last step and finish with simple hot-air drying or more sophisticated Marangoni drying. To examine the quality and uniformity of surface passivation - after cleaning and Al2O3 deposition - carrier density imaging (CDI) and quasi-steady-state photo-conductance (QSSPC) are applied. A hydrophilic surface clean that leads to improved surface passivation level is found. Si-H starting surfaces lead to equivalent passivation quality but worse passivation uniformity. The hydrophilic surface clean is preferred because it is thermodynamically stable, enables higher and more uniform ALD growth and consequently exhibits better surface passivation uniformity.

Four different types of FINs; amorphous Si (a-Si), annealed a-Si, polycrystalline Si (poly-Si) and crystalline Si (c-Si) were used to investigate the effect of interfacial strength and the length of structures on the physical cleaning window by measuring their collapse forces by atomic force microscope (AFM). A transmission electron microscope (TEM) and a nanoneedle with a nanomanipulator in a scanning electron microscope (SEM) were employed in order to explain the different collapse behavior and their forces. Different fracture shapes and collapse forces of FINs could explain the influence of the interfacial strength on the pattern strength. Furthermore, the different lengths of a-Si FINs were prepared and their collapse forces were measured and the shorter length reduced their pattern strength. Strong adhesion at the interface resulted in a wider process window while smaller dimensions made the process window narrower.

Particle removal without damage addition remains a grand challenge. Particle removal and damage addition are macroscopic effects of the cleaning technique. In order to improve the understanding of cleaning techniques like high-velocity-aerosol cleaning, these macroscopic properties need to be linked to the fundamental properties of the technique like its spray characteristics. Here we show that using the particle removal or damage addition frequency, we can estimate the fraction of droplets contributing either to particle removal or damage addition. We find that only a very small fraction of the droplets leads to damage formation. We also show that for particle removal only a very small fraction of droplets is needed, or the droplets only need to clean a very small surface area. The fraction of droplets contributing to particle removal depends on the effective area used to analyze the particle removal frequency.

The increasing complexity of semiconductor devices imposes challenging requirements on particle contamination and surface damage. To meet these requirements novel surface-cleaning processes are evaluated, which combine physical energy with organic solvents. In this work, the performance of megasonic cleaning with deionized water (DIW) and N-methylpyrrolidone (NMP) was evaluated in terms of particle removal efficiency (PRE) and damage analysis. The goal was to define an optimum process window where the PRE was maximum and the damage was minimum. Particle removal and damage analysis were performed on unpatterned silicon wafers and with patterned polysilicon lines, respectively, under identical sonic power and process parameters. A comparison between these two solvents reveals that at low sonic power the particle-cleaning performances in DIW and NMP are similar. At high sonic power, in both solvents a detailed analysis of the PRE and damage indicates a non-homogeneous trend over the surface of the wafer. Mor...

High velocity aerosol cleaning using ultrapure water or dilute aqueous solutions (e.g. dilute ammonia) is common in semiconductor IC fabrication [1]. This process combines droplet impact forces with continuous liquid flow for improved cleaning efficiency of sub-100nm particles. As with any physically enhanced cleaning process, improved particle removal can be accompanied by increased substrate damage, especially to smaller (

The removal of particles from silicon wafers without pattern damage during fabrication process is extremely important for increasing the yield. Various physically assisted cleaning techniques such as megasonic cleaning, jet spray cleaning, and laser shock wave cleaning (LSC) have been introduced. However, most of tools show pattern damage [1]. One of the main challenges in next generation cleaning process is the particle removal without the pattern damage. As the feature size continues to decrease, the patterns are so fragile that it is hard to remove particles less than 50 nm without pattern damages. To accomplish the effective cleaning performance without the damage, the collapse force of pattern and removal force of particle should be known quantitatively. In this paper, pattern collapse forces were measured for different gate stack patterns by lateral force microscope (LFM) [2]. The particle removal mechanism of LSC was studied to find the relationship between measured collapse forces and particle removal force by LSC which has a known applied force. Finally, particle contaminated pattern wafers were cleaned by LSC with optimized process parameters to verify the relationship and to achieve the best particle removal performance without the pattern damage.

As the dimensions of the structures of integrated circuits shrink, the influence of particles on device yield becomes increasingly important. According to the cleaning requirements of the International Technology Roadmap for Semiconductors (ITRS) in 2007, particles of 32 nm and larger are believed to be detrimental to devices and thus have to be removed. To remove nano-particles with minimal substrate loss and no damage requires very dilute chemistries and sufficiently gentle physical forces in a cleaning process. In this work the performance of an aerosol spray based cleaning technique is evaluated with regard to the removal efficiency of nano-particles as well as substrate loss and structural damage.

When a physical cleaning technology, such as megasonic and high-velocity-liquid aerosol cleaning, is considered for the removal of particles or photo resist residues, damage addition is a major concern. After detection of defects in long gate stack lines by bright field inspection (KT2800), SEM imaging shows they extend over a length in the order of 1μm (Figure 1) [1].

In order to obtain high yields during IC manufacturing, particles - added during layer deposition, etching … - have to be removed. In order to meet the stringent requirements set by the ITRS roadmap, this cleaning has to occur with minimal substrate etching. This necessitates the use of physically-assisted particle-removal techniques, e.g. megasonic cleaning. These methods are usually evaluated on blanket wafers. However, many cleaning steps occur on patterned wafers. The goal of this paper is to investigate the particle removal efficiency (PRE) for patterned substrates compared to blanket wafers. A full-wafer contamination and detection protocol was developed to evaluate the removal efficiencies of micron-wide trenches. The student-t test reveals a significantly lower PRE for 1μm wide by 2.2 μm deep trenches versus a blanket wafer for megasonic cleaning. This is relevant for STI cleaning and cleaning of dielectric trenches in damascene patterning.

The local particle removal efficiency (PRE) of nano particles in megasonic cleaning experiments is studied. This approach makes it possible to quantify non uniform cleaning effects over the wafer and to look into the dynamics of particle removal at different areas on the wafer. A direct correlation between PRE and megasonic induced damage of device structures demonstrates that a considerable amount of damage is already formed at less efficiently cleaned areas of the wafer.

Cleaning of nano-particles is becoming a major challenge in semiconductor manufacturing as efficient particle removal must be achieved without substrate loss and without damage to fragile structures. In this work cleaning performance and structural damage by a mixed fluid-jet technique were evaluated and directly compared to the performance of several megasonic systems. The test vehicles were hydrophilic Si wafers contaminated with 78-nm SiO2 particles and 70-nm poly-gatestack line patterned wafers. The results showed a broader process window for particle removal without damaging for the mixed fluid-jet technique compared to the megasonic systems.

Physical-cleaning technologies are usually evaluated by comparing the particle removal efficiency (PRE) on blanket wafer with damage formation on fragile structures, typically gate stack type structures. However, patterned wafers provide a more realistic cleaning challenge. Particle removal efficiencies from micron-wide and -deep trenches have been evaluated using highvelocity-aerosol cleaning. When using short cleaning times, i.e. 1 scan of approximately 5s, a decrease in cleaning efficiency is found for even modest pattern dimensions compared to blanket wafers. By extending the cleaning time, i.e. increasing the number of scans, cleaning efficiencies comparable to blanket-wafer tests can be reached. These results are compared with cleaning efficiencies obtained in a megasonic cleaning tank. Introduction Due to the stringent specifications for substrate loss [1], chemical cleaning has to be assisted by physical forces to enable the removal of particles. Recently high-velocityaerosol cleaning was shown to provide a good balance between particle removal efficiency (PRE) and damage [2] and to outperform a number of megasonic cleaning systems for the removal of 78nm silica particles versus damaging to 70nm gate-stack lines. [3] However these particle removal efficiencies are determined on blanket wafers while ‘real’ cleaning steps are performed on patterned wafers. Differences between cleaning of blanket and patterned wafers have already been studied. [4] However these patterns consisted of very large structures, where the pattern dimensions largely exceeded the cleaning-event size, i.e. the 3μm bubble radius for megasonic cleaning at 1MHz. Also recently a decrease in PRE has been shown upon megasonic tank cleaning of micron-sized features. [5] For high-velocity-aerosol cleaning the cleaning events consist of large droplets (10-100μm) impacting on the surface. [6] The cleaning mechanism for high-velocityaerosol cleaning is described by sideways jetting during the impact of a droplet on a surface. This sideways jetting is parallel to the substrate compared to the perpendicular jetting due the asymmetric collapse of a bubble during megasonic cleaning. This might suggest that the PRE of high-velocity-aerosol cleaning might be influenced even more by the presence of patterns on the wafer compared to megasonic (tank) cleaning. Experimental The particle removal efficiency (PRE) of high-velocity aerosol cleaning (DNS Nanospray) has been evaluated for 10, 3 or 1μm wide, 1 or 2.2μm deep trenches in silicon. The wafers were contaminated with 350nm large silica particles. Prior to contamination the wafers received an O3-last clean. The particles were detected using a darkfield-inspection tool (KLA-Tencor AIT). Results Figure 1 shows the PRE as a function of the aspect ratio (depth divided by width) for high-velocity-aerosol cleaning. The PRE data for the megasonic system have been taken from Ref. 5. Both cleaning techniques show a more than 10% decrease in particle removal efficiency for the 1μm wide, 2.2μm deep trenches compared to blanket wafers. Megasonic and aerosol cleaning show a similar drop in cleaning efficiency. By reducing the number of scans for high-velocityaerosol cleaning, we were able to evaluate changes in cleaning efficiency for even modest trench dimensions (aspect ratio < 1). The results show that already for these aspect ratios the particle removal efficiency for particles inside the trenches is substantially lower than on blanket wafers. However the cleaning efficiency can be recovered by extending the number of scans. Conclusion We can conclude that patterned wafers can be cleaned by high-velocity aerosols. However the removal of particles from patterned wafers proves to be more difficult than their removal from blanket wafers. References: [1] International Technology Roadmap for Semiconductors 2006 update, Front end processes, p. 9 [2] H. Hirano et al. Electrochem. Solid-State Lett., Vol. 9 (2006) p. G62 [3] G. Vereecke et al. UCPSS 2006, to be published in Solid State Technology [4] K. Bakhtari et al. J. Electrochem. Soc. Vol. 153 (2006) p. C603 [5] K. Wostyn et al. UCPSS 2006, to be published in Solid State Technology [6] S. Verhaverbeke, Sematech Surface Preparation and Cleaning Conference 2005 Figure 1: The particle removal efficiency (PRE) normalized to the PRE as determined on blanket wafers. The open circles show the results for high-velocity aerosol cleaning. The open triangles show the results for megasonic cleaning and were taken from Ref. 5.

As the semiconductor industry moves to processes for line widths of 65nm and beyond, there is the need for a new cleaning scheme addressing various new issues of the nano world. The ongoing trend to lower concentration mixtures in critical wafer cleaning now comes to its ultimate climax by reducing the concentration down to a single digit ppm level, and then to ultra low concentrations far below 1 ppm, making use of a whole new part of physics: Quantum Electro Dynamics and the formation of “clusters”. First we will outline the nature and the benign behaviour of the “clusters”. The study focuses on the inline test results of the first clustered clean application in semiconductor manufacturing environment enabling us to compare the performance of the clustered clean to the standard RCA clean of the fab. Clusters formation of ions in very dilute solutions and their physical properties has been described by Shui-Yin Lo [1,2] in 1996. Once the Megasonics energy has detached the particles off the surface, the clustered water holds the particles in the fluid as it is creating a zeta potential between the wafer surface and the now liquid borne particles. Thus, preventing a redeposition on the wafer surface, the particles now can be transported off the Processing area by overflow rinse. The scope of this work was to prove and compare the Particle Removal Efficiency (PRE) of this new cleaning method with standard RCA Clean.

The removal of particles from silicon wafers without pattern damage during fabrication process is extremely important for increasing the yield. Various cleaning techniques such as megasonic cleaning, jet spray cleaning, laser shock wave cleaning and so on are introduced to remove particles. However, most of these tools show pattern damage. One of main issues in the development of next generation cleaning process is how to clean wafers without pattern damages. As feature size continues to decrease, pattern can be easily damaged by cleaning itself which means no particle removal on the patterned wafers.. In order to secure effective cleaning process without pattern damages, the pattern collapse and particle removal force should be quantitatively understood and measured. Some groups tried to measure pattern collapse force of photoresist for improving adhesion [1, 2]. In this paper, the methods to measure the pattern collapse and particle adhesion forces were introduced and compared of interest to wafer cleaning. The pattern collapse and particle removal forces were measured by AFM (XE-100, PSIA, Korea) with XEL as nanolithography software to manipulate a cantilever and the signal access module to collect cantilever bending and torsion signals. These signals from AFM were acquired and processed by data acquisition board (PCI-6251, National Instrument, USA) and LabVIEW v8.2 software. Before measuring forces, the thickness and tip height of cantilever were measured by observing the first resonance frequency in normal direction and FESEM, respectively for theoretical calculation of a normal spring constant, kN and a torsional spring constant, kt. The angle conversion factor and the force conversion factor were calculated by a modified wedge calibration method with a calibration grating for quantifying lateral force (TGF11, Mikromash, USA). Measurements were performed in a class 100 cleanroom (R.H. 50%, Temp. 25oC). When a probe cantilever meets a structure, bending and torsion of a cantilever occur as shown in Fig. 1. If a known force is applied to the structure by a cantilever, the structure will move at a certain force as a removal force. At this moment, the torsion and bending moments will occur. If we know these moments, removal force can be obtained. In order to quantify these forces, the cantilever and AFM system should be calibrated. Especially, the contact height between the tip and pattern or particle should be known becasue the height directly relates to the torsion moment. The shape of a tip as shown in Fig. 2 is not symmetric. It is hard to define the contact point between tip and structures. However, this problem can be reduced by controlling z-feedback of AFM which controls the cantilever position during the scanning. Nanolithography software was used to control the cantilever in this purpose. As discussed previously the contact point and direction are key parameter to measure the pattern collapse force. For accurate measurements, these are carefully controlled and calibrated. When the cantilever was controlled precisely, the tip was pushed to the structure and collapsed it at a certain force as shown in Fig. 3. These signals were acquired as shown in Fig. 4. Angle conversion and force conversion factors were needed to quantify the torsion force as a removal force. To do this, structure which has known angle of slope, was used. Finally, only contact height as almost same as tip height and torsional spring constant removal force could be quantified. The force of pattern collapse and particle removal was successfully measured by AFM. These forces can provide a hand to understand removal behavior particles without pattern damages.