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Electronic Design Automation (EDA) software automates the IC design process and increases the design efficiency and capabilities. With the scaling of semiconductor technologies, the importance of EDA has rapidly increased. At the heart of most EDA design problems are combinatorial optimization problems, which are usually solved with heuristics, or analytical method in classical methods. Owing to the increasing difficulties of the EDA problems and demand for EDA tools designing increasingly complicated electronic systems, classical EDA algorithms are struggling to keep up with the ever more challenging EDA design tasks. Thus, better and more efficient EDA solutions are urgently needed to address the challenge. In recent years, there have been some major development in the field of machine learning, especially in (deep) reinforcement learning. Recent success of reinforcement learning has been demonstrated in fields including robotics, games as well as combinatorial optimization problems. This motivates us to explore the possibility of applying machine learning specifically reinforcement learning to come up with better EDA algorithms.In this research, we propose new algorithms to solve combinatorial problems in EDA based on reinforcement learning and supervised learning. To achieve this, we identified two research objectives. The first one is to developing reinforcement learning algorithms for solving EDA routing problems that performs better and more efficient than the current EDA routing solutions. Under this research objective, we propose three technical goals: (1) DQN Global Routing that solves global routing with Deep Q-learning; (2) Attention Routing that solves detailed routing with attention-based reinforcement learning; (3) Spectral DQN Routing that solves generic EDA routing and obstacle avoiding routing with combination of DQN and spectral method. Our proposed RL-based routing solutions provide better and more efficient alternatives compared with existing routing solutions. The second research objective is to develop machine-learning-based algorithm for automatic 2D space partitioning generation with island minimization objective. To achieve this, we propose the GOMLP algorithm that solves the power plane generation with supervised learning. The power plane generation, as an instance of space partitioning generation with island minimization objective has no readily available algorithms to solve. Our proposed method is the first successful attempt in developing automatic power plane generation algorithms by leveraging supervised learning. We also extend the GOMLP to solve multilayer power plane generation problems with the H-GOMLP that combines GOMLP with hierarchical clustering method.

We present an automatic multilayer power plane generation method to accelerate the design of printed circuit boards (PCB). In PCB design, while automatic solvers have been developed to predict important indicators such as the IR-drop, power integrity, and signal integrity, the generation of the power plane itself still largely relies on laborious manual methods. Our automatic power plane generation approach is based on genetic optimization combined with a multilayer perceptron and is able to automatically generate power planes across a diverse set of problems with varying levels of difficulty. Our method GOMLP consists of an outer loop genetic optimizer (GO) and an inner loop multi-layer perceptron (MLP) that generate power planes automatically. The critical elements of our approach include contour detection, feature expansion, and a distance measure to enable island-minimizing complex power plane generation. We compare our approach to a baseline solution based on A*. The A* method consisting of a sequential island generation and merging process which can produce less than ideal solutions. Our experimental results show that on single layer power plane problems, our method outperforms A* in 71% of the problems with varying levels of board layout difficulty. We further describe H-GOMLP, which extends GOMLP to multilayer power plane problems using hierarchical clustering and net similarities based on the Hausdorff distance.

Physical design and production of Integrated Circuits (IC) is becoming increasingly more challenging as the sophistication in IC technology is steadily increasing. Placement has been one of the most critical steps in IC physical design. Through decades of research, partition-based, analytical-based and annealing-based placers have been enriching the placement solution toolbox. However, open challenges including long run time and lack of ability to generalize continue to restrict wider applications of existing placement tools. We devise a learning-based placement tool based on cyclic application of Reinforcement Learning (RL) and Simulated Annealing (SA) by leveraging the advancement of RL. Results show that the RL module is able to provide a better initialization for SA and thus leads to a better final placement design. Compared to other recent learning-based placers, our method is majorly different with its combination of RL and SA. It leverages the RL model's ability to quickly get a good rough solution after training and the heuristic's ability to realize greedy improvements in the solution.