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ispartof: pages:73-76 ispartof: ESSCIRC 2022- IEEE 48TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) pages:73-76 ispartof: 48th IEEE European Solid State Circuits Conference (ESSCIRC) location:ITALY, Milan date:19 Sep - 22 Sep 2022 status: published

In this letter, a stitched array of $768\times 64$ pixels for X-ray dental imaging is presented. The sensor architecture allows to increase the frame rate up to 900 fps thanks to a pipeline approach that minimizes the deadtime between consecutive frames. A column-based ADC converts pixel values in digital form while an external FPGA performs the operation of time-delay integration accumulation, thus increasing the signal-to-noise ratio. Internal programmable gain allows to achieve a maximum sensitivity of 2.6 LSB/nGy and, at the same time, to extend the dynamic range of the sensor in case of high intensity. The final system consists of two sensors each one having a size of $74.5\times 9$ mm, assembled in a PCB and coupled with a high sensitive columnar thallium-doped cesium iodide (CsI(Tl)) scintillator for X-ray conversion. The sensor, fabricated in a standard CMOS 0.15- $\mu \text{m}$ technology with a stitching approach, shows a pixel size of 97 $\mu \text{m}$ .

This article reports the design and characterization of a 32 $\times $ 32 single-photon avalanche diode (SPAD) time-resolved image sensor for quantum imaging applications fabricated in a 150-nm CMOS standard technology. A per-SPAD time-to-digital converter (TDC) records the spatial cross correlation functions of a flux of entangled photons. Each 44.64- $\mu \text{m}$ pixel with 19.48% fill-factor features a 210.2-ps resolution, 50-ns (8-bit) range TDC with 1.28-LSB differential and 1.92-LSB integral nonlinearity (DNL/INL). The sensor achieves an observation rate of up to 1 MHz through a current-based mechanism that avoids reading empty frames when the photon rates are low. A row-skipping mechanism detects the absence of SPAD activity in a row to increase the duty cycle. These two features require only three transistors in each pixel. The sensor functionality is demonstrated in a quantum imaging experiment that achieves super-resolution.

Secondary neutrons produced in Particle Therapy (PT) treatments are responsible for the delivery of a large fraction of the out-of-target dose as they feebly interact with the patient body. To properly account for their contribution to the total dose delivered to the patient, a high precision experimental characterisation of their production energy and angular distributions is eagerly needed. The experimental challenge posed by the detection and tracking of such neutrons will be addressed by the MONDO tracker: a compact scintillating fibres detector exploiting single and double elastic scattering interactions allowing for a complete neutron four momentum reconstruction. To achieve a high detection efficiency while matching the fibres (squared, 250 $\mu$m side) high granularity, a single photon sensitive readout has been developed using the CMOS based SPAD technology. The readout sensor, with pixels of $125\times250\ \micro\meter^2$ size, will be organised in tiles covering the full detector surface and will implement an auto-trigger strategy to identify the events of interest. The expected detector performance in the context of neutron component characterisation in PT treatments delivered using carbon ions has been evaluated using a Monte Carlo simulation accounting for the detector response and the neutrons production spectra.

We propose a simulator model to estimate the performance of digital Silicon Photomultipliers (dSiPM) based on Single Photon Avalanche Diodes (SPADs) in terms of detection rate of photons incident on the sensor. The work provides guidelines for efficient array structure depending on: the number of SPADs, fill factor, area of both SPADs and array. A comparison of the main techniques present in the literature to digitally combine multiple outputs into single channel is included with simulated results showing promising higher detection rates for XOR-based dSiPMs. Mathematical expressions are derived to estimate dSiPM parameters such as maximum detection rate and detector dead time as functions of the mentioned design parameters.

We investigate the photon detection efficiency (PDE) and the dynamic range for digital silicon photomultipliers (dSiPMs) over a selection of design parameters: dSiPM unit cell dead time, PDE, unit cell area and fill factor, number of cells, and total dSiPM active area. Two receiver scaling scenarios are considered: varying the number of cells for 1) a fixed unit cell area or 2) a fixed total dSiPM area. Theoretical and simulated results are confirmed with experimental data from a selection of dSiPMs realised on a test chip in $\mathbf {130{\rm{-}nm}}$ CMOS process.

A CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8- $\mu \text{m}$ pixel pitch and 26.8% fill factor (FF) is presented. The combination of analog pixel electronics and scalable shared-well SPAD devices facilitates high-resolution, high-FF SPAD imaging arrays exhibiting photon shot-noise-limited statistics. The SPAD has 47 counts/s dark count rate at 1.5 V excess bias (EB), 39.5% photon detection probability (PDP) at 480 nm, and a minimum of 1.1 ns dead time at 1 V EB. Analog single-photon counting imaging is demonstrated with maximum 14.2-mV/SPAD event sensitivity and 0.06e− minimum equivalent read noise. Binary quanta image sensor (QIS) 16-kframes/s real-time oversampling is shown, verifying single-photon QIS theory with $4.6\times $ overexposure latitude and 0.168e− read noise.

This paper presents an efficient and robust circuital implementation of a rail-to-rail input stage with transconductance control, tailored for low-noise operational amplifiers based on differential pairs biased in the sub-threshold region. The proposed g m -control circuit design is indeed based on transistors ratio only, and allows efficient control with scaled currents and dimensions. The architecture guarantees nearly constant performance in terms of bandwidth and power consumption over the whole common mode input range in a power- and area-efficient way. The achievable precision of the transconductance control is also analyzed with transistor equations and its deviation predicted with a simple analytical model, which suggests also a strategy for the minimization of the error by proper tuning. A prototype of the input---output rail-to-rail operational amplifier has been fabricated in a standard 0.35 μm CMOS technology, confirming the validity of the g m -control loop. The amplifier consumes 597 μA from a 3.3 V supply, with an open-loop gain of 107 dB and a gain-bandwidth product of 42.6 MHz.

Single-photon avalanche diodes (SPADs) in the form of high-resolution imaging pixel arrays are used in 3D cameras, motion-tracking, biomedical and time-correlated single photon counting (TCSPC) applications. Rapid spatial and temporal zoom onto objects of interest is an attractive feature. We present here novel high-speed time-zoom functionality achieved with the digital readout mode of the TACImager, a 256 x 256 TCSPC image sensor array based on sample and hold Time to Amplitude Converter (TAC) pixels. A column-parallel flash Analogue to Digital Converter (ADC) is implemented in the TACImager to support fast digital readout, allowing per-pixel, 3-bin TCSPC histogramming at frame rates of 4 kfps. New results related to this high-speed mode of operation are presented. The TACImager utilises a global ramp voltage as a timing reference, allowing time-zoom to be achieved through dynamic adjustment of comparator voltages, ramp offset voltages and ramp waveforms. We demonstrate the influence of fixed pattern noise in the pixels and column parallel ADCs on the results.

SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed.

A recently proposed XOR-based digital silicon photomultiplier (dSiPM) is compared against the OR-based counterpart. We show experimental data from a set of single-photon avalanche diode (SPAD) pixel arrays in 130-nm CMOS process with selectable OR tree and XOR tree for direct comparison. We demonstrate how XOR-based dSiPMs solve the limitation caused by monostable circuits and reach higher maximum count rates compared with optimized OR-based dSiPMs. The increased throughput of the SPAD array allows higher sampling rates for the digitization of the light signal enhancing dynamic range and linearity.

Our recent progress in CMOS single-photon avalanche diode (SPAD) image sensors will be presented. We will highlight areas where these can compete with existing low-light imaging technologies using examples from superresolution microscopy. Article not available.

Time-correlated single photon counting (TCSPC) is a photon-efficient technique to record ultra-fast optical waveforms found in numerous applications such as time-of-flight (ToF) range measurement (LIDAR) [1], ToF 3D imaging [2], scanning optical microscopy [3], diffuse optical tomography (DOT) and Raman sensing [4]. Typical instrumentation consists of a pulsed laser source, a discrete detector such as an avalanche photodiode (APD) or photomultiplier tube (PMT), time-to-digital converter (TDC) card and a FPGA or PC to assemble and compute histograms of photon time stamps. Cost and size restrict the number of channels of TCSPC hardware. Having few detection and conversion channels, the technique is limited to processing optical waveforms with low intensity, with less than one returned photon per laser pulse, to avoid pile-up distortion [4]. However, many ultra-fast optical waveforms exhibit high dynamic range in the number of photons emitted per laser pulse. Examples are signals observed at close range in ToF with multiple reflections, diffuse reflected photons in DOT or local variations in fluorescent dye concentration in microscopy. This paper provides a single integrated chip that reduces conventional TCSPC pile-up mechanisms by an order of magnitude through ultra-parallel realizations of both photon detection and time-resolving hardware. A TDC architecture is presented which combines the two step iterated TCSPC process of time-code generation, followed by memory lookup, increment and write, into one parallel direct-to-histogram conversion. The sensor achieves 71.4ps resolution, over 18.85ns dynamic range, with 14GS/s throughput. The sensor can process 1.7Gphoton/s and generate 21k histograms/s (with 4.6μs readout time), each capturing a total of 1.7kphotons in a 1μs exposure.

A 9:8 µm pitch SPAD-based pixel is presented with a novel and scalable Sample and Hold (S/H) Time to Amplitude Converter (TAC) pixel architecture offering the potential to create high spatial resolution Time Correlated Single Photon Counting (TCSPC) image sensors in the future. This pixel pitch is an order of magnitude smaller than previous TCSPC pixels. The NMOS-only TAC performance is measured in a single point TCSPC optical experimental setup. 93ps LSB time resolution is obtained over 80ns dynamic range. Dynamic range limitations are discussed and improvements are suggested. Index Terms—SPAD, Single Photon Avalanche Diode, TAC, Time to Amplitude Converter, TCSPC, Time Corre- lated Single Photon Counting.

A 320×240 single photon avalanche diode (SPAD) based single photon counting image sensor is implemented in 0.13μm imaging CMOS with state of the art 8μm pixel pitch at 26.8% fill factor. The imager is demonstrated operating as a global shutter (GS) oversampled binary image sensor reading out at 5.14kFPS. Frames are accumulated in real time on FPGA to construct a 256 photon/8bit output image at 20FPS.