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A monitoring was conducted in 35 commercial vineyards located in Piedmont (North-West Italy) in September 2018 to test the sensitivity of Botrytis cinerea populations to the fungicides that were commonly used in the past and at present: benzimidazoles, dicarboximides, anilinopyrimidines, phenylpyrroles, hydroxyanilides and SDHI fungicides. Sensitivity was tested by evaluating the spore germination on a medium amended with a discriminatory concentration of the different tested botryticides. Conidial suspensions were prepared from infected, randomly sampled bunches and used for the tests. In comparison with the years 2008–2014, the following trend was recorded: benzimidazole resistance was quite stable and was found in about 50% of the vineyards involved in the monitoring; dicarboximide resistance had disappeared in the tested samples, while the frequency of resistance to anilinopyrimidines had increased; the resistance to fenhexamid had decreased; in the case of boscalid, the presence of resistance was quite stable; no resistance to phenylpyrroles was found, although the high discriminatory dose used for fludioxonil cannot exclude the presence in the tested vineyards of low levels of resistance to this fungicide, typical of multidrug-resistant strains.

Viticulture is a cropping system in which treatment against fungal diseases (in particular powdery and downy mildews) can be extremely frequent. Accordingly, a reduction in antimicrobial treatments and the application of environmentally-friendly compounds are becoming increasingly important for a more sustainable viticulture. In addition to their effect against pathogens, the impact of these products on the quality of the grapes is very important for the oenological industries, but unfortunately at present few data are available. We evaluated the effect of the application of biocontrol products and resistance inducers in the vineyard on the mechanical properties, microbial ecology, technological and phenolic maturity of Vitis vinifera “Nebbiolo” grapes at harvest. The yield and vigor of vines were not influenced by the treatments, nor were the production of primary and secondary metabolites. However, the active ingredients influenced the mechanical properties of the skin (hardness and thickness). A significant hardening of the skin was detected when laminarin and chito-oligosaccharides were used, and sulfur induced a thickening of the skin with potential consequences for wine quality. Furthermore, the yeast community present on grape berries was influenced by the treatments. The abundance of Aureobasidium pullulans, the dominant species on the grape berry, changed in response to the compounds used. In addition, Alternaria sp. was reduced in some treatments with a potentially positive effect on the quality and the safety of the grapes. This study provides an overview of the effect of biocontrol products and resistance inducers on microbial ecology and “Nebbiolo” grape quality, contributing to the establishment of more sustainable and effective defense strategies in viticulture.

The reduction of antimicrobial treatments and mainly the application of environmentally friendly compounds, such as resistance elicitors, is an impelling challenge to undertake more sustainable agriculture. We performed this research to study the effectiveness of non-conventional compounds in reducing leaf fungal attack and to investigate whether they influence the grape phyllosphere. Pathogenicity tests were conducted on potted Vitis vinifera &ldquo, Nebbiolo&rdquo, and &ldquo, Moscato&rdquo, cultivars infected with the powdery mildew agent (Erysiphe necator) and treated with three elicitors. Differences in the foliar microbial community were then evaluated by community-level physiological profiling by using BiologTM EcoPlates, high throughput sequencing of the Internal Transcribed Spacer (ITS) region, and RNA sequencing for the viral community. In both cultivars, all products were effective as they significantly reduced pathogen development. EcoPlate analysis and ITS sequencing showed that the microbial communities were not influenced by the alternative compound application, confirming their specific activity as plant defense elicitors. Nevertheless, &ldquo, plants were less susceptible to the disease and presented different phyllosphere composition, resulting in a richer viral community, when compared with the &ldquo, plants. The observed effect on microbial communities pointed to the existence of distinct genotype-specific defense mechanisms independently of the elicitor application.

Erysiphe necator is favourably influenced by the increase in temperatures and remains the main pathogen threatening grape in Northern Italy. In the present work, the efficacy of laminarin and calcium oxide in the control of grape powdery mildew was evaluated, comparing them to sulphur. Two tests were carried out on potted grape “Moscato” plants in 2017, and two field trials were carried out in Italy during 2016 and 2017 on a vineyard of the “Moscato” variety. Laminarin and calcium oxide showed, for the first time, to significantly reduce powdery mildew, and this occurred in all trials. However, laminarin was less effective than sulphur in potted trials and in 2016 field trial, and both laminarin and calcium oxide were less effective than sulphur in 2017 field trial.

The recent outbreak of bacterial canker on kiwifruit, caused by Pseudomonas syringae pv. actinidiae, has caused considerable damage to the international kiwifruit industry. Commercial products, and products under development, were evaluated over 2 years to assess their ability to control bacterial canker on kiwifruit under controlled conditions. The results were compared with two trials carried out in a kiwifruit orchard located in northern Italy during 2011 and 2012, to test the preventative efficacy of different copper formulations against P. syringae pv. actinidiae. In the greenhouse and orchard trials, copper hydroxide and the mixtures of copper hydroxide and copper oxychloride, significantly reduced the foliar symptoms by 70–80 % compared with the control, and showed low phytotoxicity. Similar efficacy was provided by acibenzolar-S-methyl, whose use has been temporarily extended to kiwifruit in Italy, with a maximum of four treatments per year. However, the product showed phytotoxicity on one-year old plants. The efficacy of fosetyl-Al was lower, particularly in the first orchard trials of 2012 and 2013. The efficacy of the other products tested never exceeded 30–40 %, and some products were not significantly different from the control. Kiwifruit plants grown in a steamed peat substrate mixed with compost obtained from digested organic matrices of municipal solid waste showed significantly fewer leaf spots compared with untreated controls. Copper compounds alternated with resistance inducers could be used in combination with compost, in order to develop new integrated control strategies to reduce the disease development and spread.

This investigation was undertaken to test different control strategies against Botrytis cinerea vineyards. Two commercial vineyards, "Barbera" and "Moscato," located in Piedmont (Northern Italy) were divided into seven plots and treated with different combinations of fungicides including fenhexamid, pyrimethanil, fludioxonil + cyprodinil, iprodione, and boscalid, a new carboxamide compound. An integrated strategy including a chemical (pyrimethanil) and a biocontrol agent (Trichoderma spp. t2/4ph1) was also included. At harvest, the percentage of bunches and berries attacked by B. cinerea and the concentration of the chemical fungicides were determined. All the pesticide residues at harvest were below the maximum residue level (MRL), except when two applications of pyrimethanil per season were applied. Boscalid was the most effective active ingredient against B. cinerea among the tested chemicals. When boscalid application was followed by a treatment with pyrimethanil, its efficacy was similar to that shown by two treatments of pyrimethanil. However, this second strategy was not feasible due to the risks of resistance development in the pathogen and to the residue accumulation as indicated by the analysis.

While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on dynamic voltage and frequency scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power management knob for multi-core processors. PCPG is the ability to cut the voltage supply to selected cores, thus reducing to almost zero the leakage power for the gated cores. Using a testbed based on a commercial 4-core chip and a set of real-world application traces from enterprise environments, we have evaluated the potential of PCPG. We show that PCPG can significantly reduce a processor's energy consumption (up to 40%) without significant performance overheads. When compared to DVFS, PCPG is highly effective saving up to 30% more energy than DVFS. When DVFS and PCPG operate together they can save up to almost 60%.

Simulation has historically been the primary technique used for evaluating the performance of new proposals in computer architecture. Speed and complexity considerations have traditionally limited its applicability to single-thread processors running application-level code. This is no longer sufficient to model modern multicore systems running the complex workloads of commercial interest today. COTSon is a simulator framework jointly developed by HP Labs and AMD. The goal of COTSon is to provide fast and accurate evaluation of current and future computing systems, covering the full software stack and complete hardware models. It targets cluster-level systems composed of hundreds of commodity multicore nodes and their associated devices connected through a standard communication network. COTSon adopts a functional-directed philosophy, where fast functional emulators and timing models cooperate to improve the simulation accuracy at a speed sufficient to simulate the full stack of applications, middleware and OSs. This paper describes the changes in simulation philosophy we embraced in COTSon to address these new challenges. We base functional emulation on established, fast and validated tools that support commodity OSs and complex multitier applications. Through a robust interface between the functional and timing domain, we can leverage other existing simulators for individual sub-components, such as disks or networks. We abandon the idea of "always-on" cycle-based simulation in favor of statistical sampling approaches that can trade accuracy for speed. COTSon opens up a new dimension in the speed/accuracy space, allowing simulation of a cluster of nodes several orders of magnitude faster with a minimal accuracy loss.

In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logic process based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.

Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better thermal/power scaling (many small cores dissipate less than a large and complex one), and the ease and reuse of design. This paper presents a thorough evaluation of multicore architectures. The architecture that we target is composed of a configurable number of cores, a memory hierarchy consisting of private L1, shared/private L2, and a shared bus interconnect. We consider a benchmark set composed of several parallel shared memory applications. We explore the design space related to the number of cores, L2 cache size, and processor complexity, showing the behavior of the different configurations/applications with respect to performance, energy consumption, and temperature. Design trade-offs are analyzed, stressing the interdependency of the metrics and design factors. In particular, we evaluate several chip floorplans. Their power/thermal characteristics are analyzed, showing the importance of considering thermal effects at the architectural level to achieve the best design choice.

Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric interconnect fabrics, such as networks-on-chip (NoCs), have been recently proposed. The shared memory represents one of the key elements in designing MP-SoCs to provide data exchange and synchronization support. This paper focuses on the energy/delay exploration of a distributed shared memory architecture, suitable for low-power on-chip multiprocessors based on NoC. A mechanism is proposed for the data allocation on the distributed shared memory space, dynamically managed by an on-chip hardware memory management unit (HwMMU). Moreover, the exploitation of the HwMMU primitives for the migration, replication, and compaction of shared data is discussed. Experimental results show the impact of different distributed shared memory configurations for a selected set of parallel benchmark applications from the power/-performance perspective. Furthermore, a case study for a graph exploration algorithm is discussed, accounting for the effects of the core mapping and the network topology on energy and performance at the system level.

This paper investigates optimized synchronization techniques for shared memory on-chip multiprocessors (CMPs) based on network-on-chip (NoC) and targeted at future mobile systems. The proposed solution is based on the idea of locally performing synchronization operations requiring continuous polling of a shared variable, thus, featuring large contentions (e.g., spin locks and barriers). A hardware (HW) module, the synchronization-operation buffer (SB), has been introduced to queue and to manage the requests issued by the processors. By using this mechanism, we propose a spin lock implementation requiring a constant number of network transactions and memory accesses per lock acquisition. The SB also supports an efficient implementation of barriers. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform for multiprocessor systems-on-chip (MPSoCs). Two different architectures have been explored to prove that the proposed approach is effective independently from caches and coherence schemes adopted. For an eight-processor target architecture, we show that the SB-based solution achieves up to 50% performance improvement and 30% energy saving with respect to synchronization based on the caching of the synchronization variables and directory-based coherence protocol. Furthermore, we prove the scalability of the proposed approach when the number of processors increases

This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future mobile systems. We suggest the architecture of the memory controller optimized to minimize synchronization overhead. The proposed solution is based on the idea of performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e.g. spin locks), locally in the memory. We introduce a HW module, which augments the memory controller, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For an 8-processor target architecture, we show that the proposed solution achieves up to 40% performance improvement and 25% energy saving with respect to synchronization based on the caching of the synchronization variables and directory-based coherency protocol. Furthermore, we prove the scalability of the proposed approach when the number of processors increases.

The paper introduces a dynamic branch prediction scheme suitable for energy-aware Very Long Instruction Word (VLIW) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. We define a configurable hint instruction which anticipates some static information about the upcoming branch to reduce the hardware involved in the prediction, thus, the energy consumption. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it with some well-known dynamic branch prediction techniques suitable for VLIW processors. The analyzed branch predictors are characterized by simple hardware implementations, matching the low-power characteristics of the target VLIW processors. Experimental results have been carried out on Lx, an industrial 4-issue VLIW architecture.

To study the influence of environmental conditions on sporulation of Plasmopara viticola lesions under vineyard's conditions, unsprayed vines were inspected every second or third day and the numbers of sporulating and nonsporulating lesions were counted in two North Italy vineyards in 2008 to 2010. Infected leaves were removed so that only fresh lesions were assessed at each field assessment. Sporulation was studied at two scales, across field assessments and across the seasonal population of lesions. Frequencies of sporulating lesions were positively correlated with the numbers of moist hours in the preceding dark period (i.e., the number of hours between 8:00 p.m. and 7:00 a.m. with relative humidity ≥80%, rainfall >0 mm, or wetness duration >30 min). In a receiver operating characteristic analysis, predicted sporulation based on the occurrence of ≥3 moist hours at night provided overall accuracy of 0.85. To study the time course of sporulation on lesions which were not washed by rainfall, numbers of sporangia produced per square millimeter of lesion were estimated on individual cohorts of lesions over the whole infectious period. The numbers of sporangia per square millimeter of lesion increased rapidly during the first 4 days after the beginning of sporulation and then tapered off prior to a halt; the time course of cumulative sporangia production by a lesion followed a monomolecular growth model (R2 = 0.97). The total number of sporangia produced by a square millimeter of lesion increased as the maximum temperature decreased and moist hours in the dark increased. To study the release pattern of the sporangia, spore samplers were placed near grapevines with sporulating lesions. Airborne sporangia were caught in 91.2% of the days over a wide range of weather conditions, including rainless periods. The results of this study provide quantitative information on production of P. viticola sporangia that may help refine epidemiological models used as decision aids in grape disease management programs.

This paper presents Ally, a server platform architecture that supports compute-intensive management services on multi-core processors. Ally introduces simple hardware mechanisms to sequester cores to run a separate software environment dedicated to management tasks, including packet processing software appliances (e.g. for Deep Packet Inspection, DPI) with efficient mechanisms to safely and transparently intercept network packets. Ally enables distributed deployment of compute-intensive management services throughout a data center. Importantly, it uniquely allows these services to be deployed independent of the arbitrary OSs and/or hyper visor that users may choose to run on the remaining cores, with hardware isolation preventing the host environment from tampering with the management environment. Experiments using full system emulation and a Linux-based prototype validate Ally functionality and demonstrate low overhead packet interception, e.g., using Ally to host the well-known Snort packet inspection software incurs less over-head than deploying Snort as a Xen virtual machine appliance, resulting in up to 2x improvement in throughput for some workloads.

The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate these issues, but are unable to store long activity traces. As a consequence, the cost of post-Si validation now represents a large fraction of the total design cost. This work describes a hybrid post-Si approach to validate a modern load-store queue. We use an effective error detection mechanism and an expandable logging mechanism to observe the microarchitectural activity for long periods of time, at processor full-speed. Validation is performed by analyzing the log activity by means of a diagnosis algorithm. Correct memory ordering is checked to root the cause of errors.

The latency, bandwidth, and power consumption of on-chip interconnection networks are central concerns in the design of multi- and many-core microprocessors. When the global network-on-chip (NoC) is electrical, the power consumption and the limited connectivity caused by difficulties associated with global wires will limit network performance due to power or topology constraints unless applications can be written, which only require nearest neighbor communication. This is a highly unlikely scenario, and these performance and power barriers will become more severe with shrinking process technology and increased core counts. Emerging CMOS nanophotonic technologies provide a compelling alternative to traditional all-electronic NoCs. Wire power consumption is fundamentally linear with wire length. Due to the low loss nature of waveguides, optical data transmission primarily consumes energy at the endpoints where optical to electrical (OE) and electrical to optical (EO) conversion takes place. Therefore, the energy required to transport data is relatively independent of path length for path lengths of interest for NoC-based systems. Additionally, the use of wave division multiplexing can be exploited to improve per lane bandwidth. Signal integrity limitations make this option intractable for electrical NoCs. The result is that nanophotonic NoCs can provide both higher throughput and lower power consumption than all-electrical NoCs. This chapter introduces CMOS nanophotonic technology and considers its use in photonic chip-wide networks enabling many-core microprocessors with greatly enhanced performance and flexibility while consuming less power than their electrical counterparts. It provides, as a case study, a design that takes advantage of CMOS nanophotonics to achieve ten-teraop performance in a 256-core 3D chip stack, using optically connected main memory, very high memory bandwidth, cache coherence across all cores, no bisection bandwidth limits on communication, and cross-chip communication at very low latency with cache-line granularity.

This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches. Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique. We target a CMP composed of 4 cores and 1 to 8 MB of total cache. For 4MB, the proposed techniques show a 13%, 30%, and 21% energy reduction, respectively, at the cost of 0%, 8%, and 2% performance loss. For other cache sizes the behavior is qualitatively similar.

This paper presents a multiprocessor architecture prototype on a Field Programmable Gate Arrays (FPGA) with support for hardware and software multithreading. Thanks to partial dynamic reconfiguration, this system can, at run time, spawn both software and hardware threads, sharing not only the general purpose soft-cores present in the architecture but also area on the FPGA. While on a standard single processor architecture the partial dynamic reconfiguration requires the processor to stop working to instantiate the hardware threads, the proposed solution hides most of the reconfiguration latency through the parallel execution of software threads. We validate our framework on a JPEG 2000 encoder, showing how threads are spawned, executed and joined independently of their hardware or software nature. We also show results confirming that, by using the proposed approach, we are able to hide the reconfiguration time.

We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off- and on- stack bandwidth requirements at acceptable power levels. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory-intensive workloads, while simultaneously reducing power., This edition is recompiled from proceedings of ISCA-35 (the 35th International Symposium on Computer Architecture, June 21 - 25, 2008, Beijing, China) and has minor formatting differences. 13 pages; 11 figures

This paper presents the implementation of a dual-priority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. The dual-priority microkernel is supported by a multiprocessor interrupt controller to trigger periodic and aperiodic thread activation and manage context switching. We show how the dual-priority algorithm performs on a real system prototype compared to the theoretical performance simulations with a typical standard workload of automotive applications, underlining where the differences are.1

This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each processor. The system integrates all standard DMA primitives via a fast Application Programming Interface (API) and relies on interrupts having also the possibility to manage a command list. This interface allows to program the embedded multiprocessor architecture on FPGA with simple DMAs using the same DMA techniques adopted on high performance multiprocessors with complex DMA controllers. Several experiments demonstrate the performance of our solution, allowing 57% improvement on the execution time of a selected set of benchmarks. We furthermore show how some DMA programming techniques (double and multi-buffering) can be effectively used within our platform, thus easing the design and development of the hardware and the software in a reconfigurable DMA-based environment.

This paper proposes a system-level cycle-based framework to model and design heterogeneous multiprocessor systems-on-chip (MPSoC), called GRAPES. The approach features flexibility and modularity maintaining high simulation speed despite modeling at cycle level. Intellectual property (IP) system modules can be described as C++or System C entities and they are wrapped into C++ objects, called plug-ins. Plug-ins, that are modeled by the transaction level modeling (TLM) style, are managed by the GRAPES kernel, which is the core of the simulation framework. GRAPES structural approach permits to easily model run-time reconfiguration and power modeling. Furthermore, GRAPES has been used to model and to simulate a case study: a scalable and heterogeneous MPSoC based on network-on-chip (NoC) interconnect.

Several commercial vineyards, located in Piedmont (Northern Italy), were monitored in order to evaluate the sensitivity of Botrytis cinerea Pers., the causal agent of grey mould, to five classes of botryticides: benzimidazoles, dicarboximides, phenylcarbamates, anilinopyrimidines and phenylpyrroles. Strains of B. cinerea resistant to anilinopyrimidines were easily detected, particularly in 1999, a year characterized by high disease pressure, even in vineyards not sprayed with that class of fungicides. Fludioxonil-resistance, on the contrary, was not detected. Resistance to benzimidazoles and dicarboximides was at previous observed levels. For the first time, resistance to phenylcarbamates was detected in the field. Strains of B. cinerea showing multiple resistance to benzimidazoles, dicarboximides and anilinopyrimidines and maintaining a good level of virulence, as shown by tests carried out on wounded apples, are present in Italian vineyards. Strategies in the use of the botryticides are discussed, in order to avoid a loss of disease control.

This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template architecture. Our framework permits to write a parallel application by using a shared memory model. It deals with the consistency of shared data, with no need of hardware coherence protocol, but uses a software model to properlyallsynchronize the local copies with the shared memory image. This idea can be applied both to a scratchpad-based architecture or a cache-based one. The architecture is synthesizable with standard IPs, such as the softcores and interconnect elements, which may be found in any commercial FPGA toolset.

Interrupt-based programming is widely used for interfacing a processor with peripherals and allowing software threads to interact. Many hardware/software architectures have been proposed in the past to support this kind of programming practice. In the context of FPGA-based multiprocessors this topic has not been thoroughly faced yet. This paper presents the architecture of an interrupt controller for a FPGA-based multiprocessor composed of standard off-of-the-shelf softcores. The main feature of this device is to distribute multiple interrupts across the cores of a multiprocessor. In addition, our architecture supports several advanced features like booking, broadcasting and inter-processor interrupt. On the top of this hardware layer, we provide a software library to effectively exploit this mechanism. We realized a prototype of this system. Our experiments show that our interrupt controller efficiently distributes multiple interrupts on the system.

Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a JPEG Encoder which exploits this feature. We propose a mixed HW/SW architecture, where most compute-intensive components of the application are mapped to application-specific HW cores. These cores dynamically alternate on the FPGA. Our purpose is to describe a real-world application of reconfigurable computing, illustrating how this approach allows for saving area with negligible performance overhead. We built a fully-working prototype, which demonstrates that the reconfigurable JPEG encoder achieves 29.6% area saving, 1.5% performance loss, and negligible power overhead with respect to a solution which uses statically mapped HW cores.

This paper presents the design of a JPEG encoder which exploits this feature. We propose a mixed HW/SW architecture, where most compute-intensive components of the application are mapped to application-specific HW cores. These cores can be alternated on the FPGA, by means of internal dynamic reconfiguration. Our purpose is to describe a real-world application of reconfigurable computing, illustrating how this approach allows to save area with negligible performance overhead.

Multimedia applications, and in particular the encoding and decoding of standard image and video formats, are usually a typical target for systems-on-chip (SoC). The bi-dimensional discrete cosine transformation (2D-DCT) is a commonly used frequency transformation in graphic compression algorithms. Many hardware implementations, adopting disparate algorithms, have been proposed for field programmable gate arrays (FPGA). These designs focus either on performance or area, and often do not succeed in balancing the two aspects. In this paper, we present a design of a fast 2D-DCT hardware accelerator for a FPGA-based SoC. This accelerator makes use of a single seven stages 1D-DCT pipeline able to alternate computation for the even and odd coefficients in every cycle. In addition, it uses special memories to perform the transpose operations. Our hardware takes 80 clock cycles at 107MHz to generate a complete 8times8 2D DCT, from the writing of the first input sample to the reading of the last result (including the overhead of the interface logic). We show that this architecture provides optimal performance/area ratio with respect to several alternative designs.

The starting point for the activities in MAIS concerning hardware architectures might be summarized as follows: extract the most relevant and characteristic requirements on and challenges to the hardware architecture presented by the MAIS applications, and perform an exploration of the architectural design space (at the level of both the individual processing nodes in a network and of the network itself) so as to optimize some particularly relevant figure of merit. Specifically, we have taken performance, power consumption, and robustness of security-oriented modules into account. This allowed us to propose flexible solutions for CPU architectures, whose configuration could be exploited best at run time by the intrinsic characteristics of the applications, and to derive power models and frameworks, both at CPU and at protocol level so as to model and subsequently optimize power consumption locally and at network level. Security was analyzed from, in particular the standpoint of side channel attacks, exploring DFA attacks and examining the effectiveness and cost of some proposed countermeasures.

Multicore architectures are ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better thermal/power scaling (many small cores dissipate less than a large and complex one); and, ease and reuse of design.This paper presents a thorough evaluation of multicore architectures. The architecture we target is composed of a configurable number of cores, a memory hierarchy consisting of private L1 and L2, and a shared bus interconnect. We consider parallel shared memory applications. We explore the design space related to the number of cores, L2 cache size and processor complexity, showing the behavior of the different configurations/applications with respect to performance, energy consumption and temperature. Design tradeoffs are analyzed, stressing the interdependency of the metrics and design factors. In particular, we evaluate several chip floorplans. Their power/thermal characteristics are analyzed and they show the importance of considering thermal effects at the architectural level to achieve the best design choice.

High performance multimedia applications are typical targets of today embedded systems. These applications, complex both in terms of execution flow and amount of elaborated data, can be well addressed by MultiProcessor Systems On-Chip (MPSoCs). MPSoCs are composed of simple processors and memories tightly interconnected with fast communication channels and customized IP cores for the most demanding functions can be implemented and attached to these systems to enhance performance even more. Reconfigurable devices, like FPGA, can act as a target, even programmed at runtime, for the custom IP cores, or as a prototyping platform for the whole system. Image compression, like JPEG2000, can benefit very much from this approach and this type of architectures. This paper shows how the most demanding task of the JPEG2000 compression algorithm, the two-dimensional discrete wavelet transform, can be hardware accelerated and implemented in a MultiProcessor System-on-Chip prototyping platform on Field Programmable Gate Array (FPGA), CerberO. Architectures with different number of processors and hardware accelerators, shared among the processors or dedicated, have been implemented. To validate the approach, we show some experimental results on the platform with the hardware and the software implementation of the transformation.

This paper presents a new attack against a software implementation of the Advanced Encryption Standard. The attack aims at flushing elements of the SBOX from the cache, thus inducing a cache miss during the encryption phase. The power trace is then used to detect when the cache miss occurs; if the miss happens in the first round of the AES then the information can be used to recover part of the secret key. The attack has been simulated using the Wattch simulation framework and a simple software implementation of AES (using a single table for the SBOX). The attack can be easily extended to more sophisticated versions of AES with more than one table. Eventually, we present a simple countermeasure which does not require randomization.

In this paper is proposed a technique to integrate and simulate a dynamic memory in a multiprocessor framework based on C/C++/SystemC. Using host machine's memory management capabilities, dynamic data processing is supported without compromising speed and accuracy of the simulation. A first prototype in a shared memory context is presented., Submitted on behalf of EDAA (http://www.edaa.com/)

Main goal of the paper is introducing a dynamic branch prediction scheme suitable for energy-aware VLIW (Very Long Instruction Word) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. Experimental results have been carried out on Lx/ST200, an industrial 4-issue VLIW architecture. We gathered two sets of results: First, by introducing the proposed low-power branch prediction technique in the Lx processor, which features fully static branch prediction, a significant improvement of the energy-delay metric has been observed. Second, we evaluated filtering efficacy of the proposed method and we found that it gets an access reduction to the branch prediction unit of 93% with respect to a processor directly derived from Lx, featuring cycle-by-cycle prediction, corresponding to an average 9% energy reduction of the whole processor power budget.

Previous works have shown that neural branch prediction techniques achieve far lower misprediction rate than traditional approaches. We propose a neural predictor based on two perceptron networks: the Combined Perceptron Branch Predictor. The predictor consists of two concurrent perceptron-like neural networks, one using as inputs branch history information, the other one using program counter bits. We carried out experiments proving that this approach provides lower misprediction rate than state-of-the-art conventional and neural predictors. In particular, when compared with an advanced path-based perceptron predictor, it features 12% improvement of the prediction accuracy.

This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future power-efficient systems. The proposed solution is based on the idea of locally performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e. g. spin locks). We introduce a HW module, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For 8-processor target architecture, we show that the proposed solution achieves up to 40% performance improvement and 30% energy saving with respect to synchronization based on directory-based coherence protocol.