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Scyliorhinus canicula, also known as small-spotted catshark, is an elasmobranch worldwide distributed and in some areas of Mediterranean basin represents the most abundant elasmobranches species. This species is extensively fished and marketed throughout Europe, however despite its economic relevance, the conservation status, the biology and pathology of this elasmobranchs species are poorly investigated. Goal of this study was to investigate the metazoan fauna ofS. caniculacaught in the Mediterranean Sea. During the study period a total of 86 specimens ofS. caniculawere caught and examined.Of the 86 examinedS. canicula,81 (94.2%) tested positive for parasites presence. Two parasitic taxa were identified, the nematodeProleptus obtusus(93%) and the cestodeEutetrarhynchus ruficollis(2.3%). The high prevalence ofP. obtususobserved in the present study is similar to those observed in Ireland, United Kingdom and Spain. Noteworthy, for the first time the cestodeE. ruficolliswas retrieved in specimens ofS. canicula.

The John Dory Zeus faber is a cosmopolitan fish species of important commercial value, distributed in Eastern Atlantic, Western Pacific, Indian Ocean, and Mediterranean and Black Seas. The aim of this study was to assess the parasite fauna of John Dory fish captured in the Mediterranean Sea. Four taxa of parasites were identified, such as the leech Calliobdella sp. (1 out of 139, 0.72%), the copepods Chondrachantus zei (1 out of 139, 0.72%), nematode larvae genetically identified as Anisakis pegreffii (114 out of 139, 82%) and a bothriocephalid tapeworms (3 out of 139, 2.15%). Anisakis pegreffii proved to be the most frequent parasite. Noteworthy, the presence of the adult bothriocephalid tapeworm was described for the first time in Z. faber. Some pathological effects due to parasites and the potential zoonotic risks were also discussed.

Noise signals are needed for test and validation of electronic systems and communication channels. Available noise sources are however limited to wide band white noise sources while the arbitrary waveform generators are poorly suited for the generation of long random or pseudo random noise sequences. The paper explores the possibility of using a single bit pseudo random sequence, filtered with a FIR filter, for the generation of an analogue noise signal with programmable spectral features. The results show that the technique is suitable for real time applications. When implemented on a Field Programmable Gate Array device, the technique uses less resources compared with the state of the art.

In this paper, we investigate the avalanche behavior of field-stop insulated gate bipolar transistors (IGBTs) by means of analytical and theoretical considerations, supported by ad hoc numerical simulations. A physical explanation of the presence of negative differential resistance branches in the avalanche I-V curve of the IGBT is presented and design criteria are derived to reduce and eventually eliminate this effect.

Il testo è destinato ai laureandi in Ingegneria Elettronica ed ai laureandi in Ingegneria Informatica, finalizza le conoscenze acquisite durante i corsi di base di elettronica digitale e permette di sviluppare un sistema elettronico digitale completo. Le tecniche di progetto presentate sono di validità generale e si applicano alla progettazione della maggioranza dei sistemi elettronici digitali. Quando si arriva all'implementazione ed agli esperimenti, le metodologie sono invece particolarizzate per la realizzazione di sistemi digitali che utilizzano circuiti programmabili di tipo FPGA e CPLD. Tali dispositivi coniugano tempi di sviluppo ridotti e bassi costi e sono la scelta progettuale che più rapidamente si sta diffondendo. Dispositivi di tipo FPGA sono la scelta d'elezione sia per lo sviluppo di prototipi, sia per la realizzazione di prodotti aventi diffusione nell'ordine della migliaia di pezzi. I concetti dell'elettronica digitale sono calati in un flusso di progetto che, partendo dalle specifiche e utilizzando di volta in volta le tecniche più adatte, affronta tutti gli aspetti della progettazione. Il testo affronta le tecniche di progetto di circuiti combinatori, aritmetici, sequenziali e delle macchine a stati finiti. Una parte del testo è inoltre dedicata ai problemi di interfacciamento ed alla temporizzazione dei circuiti sincroni. Le tecniche di progetto spiegate utilizzano sia la metodologia degli schemi elettronici sia la descrizione mediante linguaggi HDL. Il linguaggio HDL spiegato ed utilizzato è il Verilog. Del linguaggio si presentano i costrutti fondamentali ed una serie di regole di utilizzo che permettono la realizzazione di circuiti digitali efficienti ed affidabili.

The superjunction concept allows the design of power semiconductor devices with improved performances compared to conventional sustaining layers. Due to the lack of accurate analytical models to characterize superjunction devices the design phase is still based on numerous and time consuming finite element simulations. In this paper a closed form analytical solution for the calculation of the breakdown voltage of a superjunction symmetric and charge balanced diode, is presented. The calculation of the breakdown voltage is based on the approximated solution of the ionization integral. The proposed solution is based on the Taylor expansion coupled with Newton Raphson algorithm.

Two-dimensional analytical models for the calculation of the electric field distribution in superjunction power semiconductor devices are presented in this paper. The models show how to analytically calculate the electric field in superjunction devices and give a deep insight in the design of superjunction structures. Numerical two-dimensional simulations validate the proposed models.

The paper presents a one dimensional model for the duration of the increased breakdown voltage phase in Deep Depletion power devices. The model includes the effect of bulk generation and space charge generation that is verified against numerical simulations of a nSi-BOX-pSi structure. The fi- nal result of the model, the duration of the high breakdown voltage phase as a function of device characteristic and the applied voltage, is verified against experimental results regarding the duration of the increased breakdown voltage phase in a power LDMOS in SOI technology. The results show that the interface states are probably the limiting factor for the duration of the increased breakdown voltage phase.

Many vertical IGBT models are currently available. They have also been implemented in commercial simulators and describe device behavior both in steady-state and transient. However, no reliable device models have been proposed for the Lateral IGBT that is widely used in the field of smart power integrated circuits. In this paper a complete physical model for the Lateral IGBT fabricated in Silicon On Insulator technology is developed. The model is implemented in Pspice circuit simulator. Model results are compared against finite element device simulation. A comparison with the most common vertical IGBT Pspice model shows that vertical IGBT models are not able to correctly predict lateral IGBT behavior.

The paper presents an analytic bidimensional model for breakdown voltage of recently proposed superjunction structures. The bidimensional model is able to correctly estimate electric field and breakdown voltage giving an insight in optimal design of superjunction devices. Further, in the paper it is shown that simplified formulas based on one-dimensional approximations overestimate breakdown voltage up to a factor two.

Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flipflops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.