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A high equivalent isotropic radiated power (EIRP) active phased array antenna system has been designed and experimentally verified at the 28 GHz band. The phased array employs Gallium Nitride (GaN) based radio frequency front-ends with 31 dBm output power in transmit mode and 3.5 dB noise figure in receive mode. A fully metallic gapwaveguide technology has been employed in order to achieve an efficient heat dissipation per aperture area of the array as well as low-loss array antenna elements that are easily manufactured. The phased array is realized by sub-arraying an 8×8 slot array antenna with horizontal polarization. The presented antenna system is capable of analog beamforming in the range of ±60 degrees in E-plane. The presented high-bandwidth phased array antenna system is a potential candidate for high power and compact size 5G base station antennas for wireless communications requiring high temperature stability at the millimeterwave bands.

Publisher Copyright: Author This paper focuses on the design aspects of the key components for a scalable phased-array system over the 200 GHz frequency range. A high-gain phase shifter chain for 220 to 240 GHz frequency range and a high-gain power amplifier (PA) with a high output power are designed in a 0.13-μm SiGe BiCMOS technology. The phase shifter chain includes a low-noise amplifier (LNA), a vector modulator phase shifter (PS), and a gain-enhancing amplifier. The LNA is a five-stage cascode design. The vector modulator core is realized by two variable gain amplifiers based on the Gilbert cell architecture. A four-stage cascode design is used for the gain-enhancing amplifier. The phase shifter chain shows a measured gain of 18 dB at 230 GHz with a 360° phase tuning range and more than 10 dB of gain control. The chip achieves a minimum measured noise figure of 11.5 dB at 230 GHz and shows a wideband noise characteristic. The complete phase shifter chain chip consumes a dc power of 153 mW and occupies a 1.41 mm2 area.A high-power PA that is critical for a large phased-array system is designed. This paper presents a unique 4-way power combining technique utilizing a differential quadrature coupler. The realized balanced PA occupies an area of 0.67 mm2 and shows a measured peak gain of 21 dB at 244 GHz. The PA consumes 819 mW of dc power and delivers a maximum saturated output power (Psat) of 7.1 dBm at 244 GHz and more than 4.3 dBm of Psat from 230 to 255 GHz.

Multi-band (MB) technology arises as a suitable solution to increase capacity within future 6G networks, while efficiently utilizing the already deployed optical fiber infrastructure. Indeed, the adoption of MB sliceable bandwidth/bit rate variable transceivers (S-BVTs) based on multi carrier modulation (MCM) enables transmission within multiple bands beyond C-band, providing sustainable capacity growth and hyper-scalability. Different slices/bands can be suitably activated in a pay-as-you grow approach according to the network demand and requirements. Additionally, the proposed MB S-BVT architecture also enables disaggregation and programmability by the adoption of an open software-defined networking (SDN) paradigm. A proof of concept of the proposed MB S-BVT is numerically and experimentally evaluated. Specifically, the transmission of 25 GHz signals/slices working at C-, L- and S-band is considered without any filtering and amplification stages. About 70 Gb/s capacity per slice/band is achieved in B2B configuration. The data rate decreases after 50.47 km, enabling maximum capacities per slice of 26.2 Gb/s (C-band) and 21 Gb/s (L- and S-bands). Additionally, the proposed MB S-BVT can be envisioned to serve different classes of services/applications over different network segments, prepared to support MB technology, thanks to the exploitation of differently performing slices/bands. © 1983-2012 IEEE.

This article proposes a methodology to ensure linear amplification of a load modulated balanced amplifier (LMBA) while keeping the power efficiency as high as possible over a frequency band ranging from 1.8 to 2.4 GHz and where the transmitted signals can present different bandwidth (BW) configurations. The proposed reconfigurable linearization methodology consists of, in a first step, tuning some free parameters (with dependence on the signal BW and frequency of operation) of the LMBA to trade-off linearity and power efficiency. In a second step, two multipurpose adaptive digital predistortion (DPD) linearizers are considered, properly combined with crest factor reduction (CFR) techniques, to meet the required linearity specifications. Either a DPD based on artificial neural networks or a DPD based on polynomials can be selected taking into account the compromise between computational complexity and linearization performance. Experimental results will validate the proposed methodology to guarantee the linearity levels (ACPR < -45 dBc and EVM < 1%) with high power efficiency in an LMBA under dynamic transmission, where both the signal BW (from 20 and up to 200-MHz instantaneous BW) and frequency of operation (in the range of 1.8-2.4 GHz) change. This work was supported in part by the Spanish Government (Ministerio de Ciencia, Innovación y Universidades) and FEDER (Fondo Europeo de Desarrollo Regional) under Grant TEC2017-83343-C4-2-R and in part by the Generalitat de Catalunya under Grant 2017 SGR 813. This paper is an expanded version from the International Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits (INMMiC), Cardiff, United Kingdom, July 2020.

This paper presents a technique to mitigate multiple access interference (MAI) in multicarrier code division multiple access (MC-CDMA) wireless communications systems. Although under normal circumstances the MC-CDMA system can achieve high spectral efficiency and resistance towards inter symbol interference (ISI) however when exposed to substantial nonlinear distortion the issue of MAI manifests. Such distortion results when the power amplifiers are driven into saturation or when the transmit signal experiences extreme adverse channel conditions. The proposed technique uses a modified iterative block decision feedback equalizer (IB-DFE) that uses a minimal mean square error (MMSE) receiver in the feed-forward path to nullify the residual interference from the IB-DFE receiver. The received signal is re-filtered in an iterative process to significantly improve the MC-CDMA system’s performance. The effectiveness of the proposed modified IB-DFE technique in MC-CDMA systems has been analysed under various harsh nonlinear conditions, and the results of this analysis presented here confirm the effectiveness of the proposed technique to outperform conventional methodologies in terms of the bit error rate (BER) and lesser computational complexity. Dr. Mohammad Alibakhshikenari acknowledges support from the CONEX-Plus programme funded by Universidad Carlos III de Madrid and the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No. 801538. Also, this work was supported by Project RTI2018-095499-B-C31, funded by the Ministerio de Ciencia, Innovación y Universidades, Gobierno de España (MCIU/AEI/FEDER, UE).

This paper presents a design methodology for a load modulated balanced amplifier (LMBA) focusing on AMPM distortion mitigation. By introducing second harmonic control as a degree of design freedom, a complex load trajectory can be selected to compensate for AMPM nonlinearities in the device without substantially affecting efficiency. A mathematical derivation is accompanied by a design procedure based on closed-form equations to fabricate an LMBA based solely on load-pull data. The theory is validated through the measured comparison of three different designs operating at 2.4 GHz in a pseudo-RF-input Doherty-like LMBA configuration, with class-J, -B, and -J* main PAs. The class-J prototype outperforms the other designs with 54% and 49% drain efficiency at peak output power and 6-dB back-off, respectively, and only 4 degrees of AM-PM across this power range. When driven with a 10-MHz, 8.6-dB PAPR LTE signal, 40.5% average efficiency is achieved with better than $-40.5$ dBc ACLR without digital predistortion.

This paper presents the design of a Ka-band active transmitarray consisting of radiating waveguide elements, a transition from waveguide to PCB, and commercial phase shifters and high-power amplifiers. A unit cell design is presented, which at a size of (0.7λ)2 allows for beamsteering without grating lobes up to around ±20° from broadside. The modeled performance of a 68-element array is presented, demonstrating the feasibility of a 81.6 dBm EIRP at 35 GHz from a 7 cm wide aperture.

This paper presents the design of a Ka-band active transmitarray consisting of radiating waveguide elements, a transition from waveguide to PCB, and commercial phase shifters and high-power amplifiers. A unit cell design is presented, which at a size of (0.7λ)2 allows for beamsteering without grating lobes up to around ±20° from broadside. The modeled performance of a 68-element array is presented, demonstrating the feasibility of a 81.6 dBm EIRP at 35 GHz from a 7 cm wide aperture.

This paper presents the design of a Ka-band active transmitarray consisting of radiating waveguide elements, a transition from waveguide to PCB, and commercial phase shifters and high-power amplifiers. A unit cell design is presented, which at a size of (0.7λ)2 allows for beamsteering without grating lobes up to around ±20° from broadside. The modeled performance of a 68-element array is presented, demonstrating the feasibility of a 81.6 dBm EIRP at 35 GHz from a 7 cm wide aperture.

Trading between transmit waveform quality and power efficiency is one of the most challenging issues in radio transmitter implementation. To this end, digital predistortion is the de-facto solution for mitigating power amplifier (PA) nonlinear distortion in cellular base-stations due to its high flexibility and good linearization performance. Theoretically, it is convenient to describe predistorter (PD) transfer function as the mathematical inverse of the PA transfer function, and PD modeling is often performed through parametric methods. Thus, an additional feedback loop is required in the system for PD model parameter estimation. PA is an analog device and DPD is a part of digital front-end, implying that PA output signal is needed to be downconverted to baseband and sampled in the parameter estimation path. Consequently, it is required to employ additional components in the feedback loop such as attenuator, downconverter, and analog-to-digital converter (ADC). In order to be able to capture higher order nonlinearities, it is necessary to perform upsampling operation, which implies that in addition to digital-to-analog converters (DACs) in the forward loop, the components in the feedback loop should support higher bandwidths than the original transmission bandwidth. Additionally, to have a good linearization performance, a high resolution ADC is required. Having an ADC/DAC that supports wide bandwidth and has high resolution is directly increasing the material cost and power consumption. When future millimeter-wave (mmWave) systems are considered, adopting DPD becomes even more complex and costly due to wider waveform bandwidths and employing active antenna arrays. Alternative to DPD, receiver based approaches, referred to as digital post-distortion (DPoD), can be utilized to mitigate the nonlinear effects of transmitter PA. Naturally, receiver side techniques do not provide any improvement in terms of out-of-band (OOB) emission issues, rather they aim to improve received signal error vector magnitude (EVM). As the radiated power at mmWave is typically EVM limited and OOB emission requirements are relaxed compared to sub-6 GHz band, DPoD can offer means for improved network energy-efficiency. Several iterative DPoD methods are proposed in the literature such as power amplifier nonlinearity cancellation (PANC), and reconstruction of distorted signals (RODS). In this thesis, we present a non-iterative computationally efficient receiver side nonlinearity mitigation technique, referred to as digital post-inverse (DPoI), along with the parameter estimation approach targeting existing 5G NR standard-compliant reference signal. The receiver EVM performance of presented approach is analyzed by using computer simulations. It is seen that DPoI can reach similar or improved performance compared to the iterative PANC method, which is chosen as a reference DPoD method. Moreover, it is shown that both DPoD methods overperform ideally linearized transmitter PA under strong nonlinear conditions, which allows higher power efficiency when receiver side techniques are employed.

In recent years, there has been a need to increase the capacity and speed of information transmission, so the communication signals used in mobile communications have been improved to meet the expectations. This will be even more significant in future 5G systems, since due to the high expansion of wireless devices, current 4G systems are starting to push their limits, where only small improvements can be achieved. Which complicates the design of transmitters, since these new signals have a wider bandwidth and a large variation between their average and peak value, causing amplifiers to operate most of the time in a zone where they are not as efficient. For this reason, amplifier architectures not only aim to have high efficiency when operating at maximum signal excursion, but also to increase efficiency in the zone where they will operate most of the time. For this purpose, there are architectures based on supply voltage modulation and load modulation to improve the efficiency at lower powers. This work addresses load modulation architectures, where Doherty and Chireix are the most prominent. In addition, with the increase in digital signal processing capabilities, new amplification architectures based on the load modulation technique have recently been proposed, but instead of using only one RF input, they use two independent digitally controlled inputs. This dissertation aims at implementing a Doherty-Chireix amplifier with two digital inputs to achieve efficient amplification for the 1.7 to 2.4GHz frequency band. In the end it was possible to design and implement a Doherty-Chireix power amplifier, with 700MHz bandwidth, with a gain between 13.9-11.3dB, a maximum power of 45dBm, a PAE of over 60% and peak-to-average power ratio between 5.2-4.1dB. Nos últimos anos, tem havido uma necessidade de aumentar a capacidade e velocidade de transmissão de informação, deste modo os sinais de comunicação utilizados nas comunicações móveis têm evoluído por forma a corresponder as expectativas. Tal será ainda mais significativo nos futuros sistemas 5G, já que devido à elevada expansão de dispositivos sem fio, os atuais sistemas 4G estão a começar a atingir os seus limites, onde apenas pequenas melhorias podem ser alcançadas. Isto vem complicar o projeto dos transmissores, uma vez que estes novos sinais apresentam uma maior largura de banda e uma grande variação entre o seu valor médio e de pico, fazendo com que os amplificadores operem na maior parte do tempo numa zona em que não são tão eficientes. Por esta razão, as arquiteturas de amplificação nos dias de hoje não só visam ter um grande rendimento quando operam com a máxima excursão de sinal, mas também o aumento do rendimento na zona onde irão operar a maior parte do tempo. Nesse sentido existem arquiteturas baseadas em modelação de tensão de alimentação e modelação de carga de modo a melhorar a eficiência a potências mais baixas. Neste trabalho são abordadas arquiteturas de modulação de carga, onde Doherty e Chireix são as que mais se destacam. Para além disso, com o aumento da capacidade de processamento digital de sinal, recentemente foram propostas novas arquiteturas de amplificação que se baseiam nestas técnicas, mas em vez de utilizar apenas uma entrada de RF, usam duas entradas independentes controladas digitalmente. Esta dissertação visa a implementação de um amplificador Doherty-Chireix com duas entras digitais de modo a obter uma amplificação eficiente para uma banda de frequências de 1.7 a 2.4GHz. No final foi possível projetar e implementar um amplificador de potência Doherty-Chireix, com 700MHz de largura de banda, com um ganho compreendido entre 13.9-11.3dB, potência máxima de 45dBm, uma PAE superior a 60% e peak-to-average power ratio entre 5.2-4.1dB. Mestrado em Engenharia Eletrónica e Telecomunicações

Modern wireless communications are pushing the limits of data rate and communication bandwidth needs. With the appearance of new services, users are expected to increase their data usage and access to services, requiring instantaneous response time. To that extent, 5G and future wireless technologies are in the race for high data rate communications, low-latency and connectivity of billions of things, offering new services for users. However, these improvements lead to key challenges, namely sustainability, energy efficiency and overall system complexity. Looking at the future, it appears that for 6G technology, these challenges will become primordial. Specifically, particular attention shall be paid to offer a sustainable design and development of transmitters and receivers hardware components, which are exhibiting key issues about energy consumption. Thus, the design of transceivers must be rethought to put forward low-complexity and sustainable solutions.In this thesis, our objective is to enhance the power efficiency of radio-frequency power amplifiers, leading to a high global system energy efficiency. Indeed, the power amplifier represents the most power hungry hardware component of the transmitter chain. Then, its power efficiency must be maximized to improve global carbon footprint. Nonetheless, this hardware component exhibits strong nonlinearities when operated close to its saturation, where its power efficiency is high. Therefore, we focus on digital pre-distortion approach to linearize the power amplifier and improve its power efficiency. To propose an efficient linearizing module, deep learning, neural networks, solutions have emerged as they offer robustness and reliability to solve nonlinear problems. However, neural networks and particularly applied to digital pre-distortion are facing several issues which represent a bottleneck. Complexity, adaptivity and energy efficiency are the main aspects that a pre-distortion module must take into consideration to be robust. These represent the main challenges of neural networks in this use case. To address these challenges, we propose in this thesis, a novel design of digital pre-distortion based on neural networks to linearize efficiently a power amplifier.To achieve such goal, this thesis is structured on three main axes. (1) First, we propose a fully customized architecture of neural networks dedicated to perform digital pre-distortion. By doing so, we think differently from the ``blackbox'' architecture design and drastically lower the complexity of the digital pre-distortion module. By breaking down the complexity, we are able to offer a cost-effective digital pre-distortion. (2) Second, we investigate approaches to deal with the time-varying effects that may affect the power amplifier, such as the temperature or electrical variations. Usually, neural networks have a poor capacity to adapt to unseen events during their training. Then, to improve the adaptivity of our solution, we choose to use a new class of learning algorithms called meta-learning. Using the latter, we demonstrate that with few data and calibration time, our proposed digital pre-distortion is able to deal with time-varying power amplifiers, with satisfying results for real-world applications. (3) Third, we further optimize our module by considering hardware implementation aspects. We propose to perform quantization on our neural networks to improve the computing resource usage and lower the energy consumption. This step is crucial to propose a hardware implementation since we would like to optimize the computing load and energy efficiency of the system. To avoid the noise induced by the quantization operation, we learn our model how to mitigate this noise by using a quantization aware training. Our results show that our quantized digital pre-distortion has the same performance as without quantization, and presents the same complexity as the implementation of a fast Fourier transform.; Les technologies de communications sans-fil modernes repoussent les limites actuelles en termes de débit et bande passante. En effet, l'apparition de nouveaux services impose un débit et accès fortement accrus. La 5G et les technologies de communications futures font l'objet d'une course au haut-débit, à la faible latence et à la connexion de milliards d'objets. Cependant, de telles améliorations impliquent pléthore de défis à relever tels que la durabilité, l'efficacité énergétique, et la complexité des systèmes. A long terme, il semble que pour la 6G, ces défis deviendront primordiaux. En l'occurrence, une attention particulière devra être portée à la conception durable des éléments matériels constituant les transmetteurs et récepteurs sans-fil. Ainsi, il convient de repenser leur conception pour mettre avant des solutions basse complexité et durables.Cette thèse a pour objectif d'améliorer l'efficacité énergétique des amplificateurs de puissance radiofréquence. L'amplificateur de puissance est le composant le plus énergivore de la chaine de transmission radiofréquence. Ainsi, son efficacité énergétique doit être maximisée pour améliorer l'empreinte carbone du système. Mais, ce composant matériel présente des non-linéarités quand il est utilisé proche de sa saturation, zone où son efficacité est maximale. Par conséquent, dans cette thèse, nous nous intéressons à la pré-distorsion numérique pour linéariser l'amplificateur de puissance, et ainsi améliorer son efficacité énergétique. Afin de proposer un module de linéarisation efficace, des techniques d'apprentissage profond, reposant sur des réseaux de neurones, sont considérées. En effet, elles offrent une certaine robustesse et fiabilité pour résoudre des problèmes non linéaires. Toutefois, les réseaux de neurones et particulièrement appliqués à la pré-distorsion numérique, présentent plusieurs problèmes. La complexité, l'adaptabilité et l'efficacité énergétique sont les principaux aspects à prendre en compte pour concevoir une pré-distorsion efficace ; ces derniers faisant défaut aux réseaux de neurones. Pour traiter ces défis, nous proposons une nouvelle conception de pré-distorsion numérique basée sur des réseaux de neurones pour linéariser efficacement l'amplificateur de puissance.Pour atteindre un tel but, cette thèse se construit autour de trois grands axes. (1) Tout d'abord, nous proposons une architecture de réseaux de neurones spécifique et dédiée à la conception d'une fonction de pré-distorsion. Ce faisant, nous améliorons drastiquement la complexité de cette dernière. (2) Ensuite, nous abordons des approches permettant de faire face aux contraintes temporelles qui influent sur l’amplificateur de puissance. On peut notamment citer des effets relatifs à la température et variations électriques du composant. Généralement, les réseaux de neurones sont peu performants lorsqu'ils doivent s'adapter à des événements inconnus de leur apprentissage. Ainsi, pour améliorer l’adaptabilité de notre solution, nous employons une classe d'algorithmes nommée "méta-apprentissage". Par ce biais, nous démontrons que notre système peut s'adapter en utilisant peu de données et temps de calibration avec des résultats satisfaisants, permettant ainsi son usage en condition réelle. (3) Finalement, nous optimisons notre module en vue d’une implémentation matérielle. Spécifiquement, nous proposons d'agir sur la quantification de nos réseaux de neurones pour améliorer leurs consommations en ressources et énergie. Cette opération s’avère cruciale pour une implémentation où les ressources s'avèrent limitées. Pour éviter le bruit induit par la quantification, nous apprenons à notre solution comment l'atténuer. Nos résultats montrent que l’emploi de la quantification n'altère pas les performances du système. De plus, la solution quantifiée présente la même complexité matérielle qu'une transformée de Fourier.

In this paper, a novel way for dual-band power amplifiers (PA) linearization is proposed based on spiking neuron networks (SNN). A dual-input dual-output SNN is interacted with classical memory polynomial model, which can largely reduce the computational complexity. The experimental results on a real PA show that the proposed method can reach similar linearization performance compared with traditional methods but with low energy consumption. This is the first time that the SNN is deployed for multi-band PA linearization. Future work is to develop a trainable SNN model for real-time PA linearization.

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. In 5G and beyond radios, the increased bandwidth, the fast-changing waveform scenarios, and the operation of large array multiple-input multiple-output (MIMO) transmitter architectures have challenged both the polynomial and the artificial neural network (ANN) MIMO adaptive digital predistortion (DPD) schemes. This article proposes training data selection methods and dimensionality reduction techniques that can be combined to enable relevant reductions of the DPD training time and the implementation complexity for MIMO transmitter architectures. In this work, the combination of an efficient uncorrelated equation selection (UES) mechanism together with orthogonal least squares (OLS) is proposed to reduce the training data length and the number of basis functions at every behavioral modeling matrix in the polynomial MIMO DPD scheme. For ANN MIMO DPD architectures, applying UES and principal component analysis (PCA) is proposed to reduce the input dataset length and features, respectively. The UES-OLS and the UES-PCA techniques are experimentally validated for a 2×2 MIMO test setup with strong power amplifier (PA) input and output crosstalk. This work was supported in part by the MCIN/AEI/10.13039/501100011033 under Project PID2020-113832RB-C22 and Project PID2020-113832RB-C21; and in part by the European Union-NextGenerationEU through the Spanish Recovery, Transformation and Resilience Plan, under Project TSI-063000-2021-121 (MINECO UNICO Programme).

This article reviews the current state-of-the-art of active-integrated antennas co-designed with power amplifiers (PAs). Three strategies to improve output power and power-added efficiency are described using examples, namely direct matching between PA and antenna, tuning of harmonic reflections in the antenna, and in antenna power combining from multiple PAs. An outlook is given on the challenges to be faced in the application of these strategies in wide-scanning phased arrays.

The objective of this project is the design and construction of a Class D power amplifier for audio signal amplification, based on the knowledge obtained in the Telecommunication Systems degree, specially in the topics of electronics and signal theory. The project is structured in three differentiated parts. In the first place, the theoretical bases necessary for the elaboration of the design are presented: description of the audio signal, preamplifiers, review of the different classes of linear power amplifiers, detailed analysis of the Class D switched power amplifier and review of different digital processing techniques, specifically equalization and digital predistortion. Next, a design of a Class D switched power amplifier made with commercial components is proposed. The design is composed of a microcontroller, a DAC, a PWM modulator, a NOT gate, a power stage and a low-pass demodulation filter. The working principle of each component is analyzed and all the necessary calculations are made. Simulations are performed at the block and circuit level. Finally, the necessary components are acquired and a real prototype is built on protoboards following the previous design. The correct operation of each block and of the total system is checked through oscilloscope measurements. The system is equalized and the performance of the prototype is measured. The project has a practical approach and supposes a personal introduction to audio electronics.

—A novel application utilizing the load-modulated balanced amplifier (LMBA) principle to actively absorb individual out-of-band intermodulation components at the output of a power amplifier operating in high compression is presented. The system requires nearly the same amount of additional power as the IMD power it absorbs, making it very efficient. It retains the power conservation properties of the LMBA and achieves linearization at a very low power and complexity penalty.

High-resolution gradient power amplifiers are required to generate high-fidelity gradient fields in magnetic resonance imaging (MRI) systems. Various aspects of gradient power amplifiers have been the subject of research in the past years, however, systematic analysis and design methods for its resolution improvement have not been sufficiently addressed. This article addresses this research gap with comprehensive analysis and design methods for resolution improvement. First, a method for systematic resolution characterization of the MRI gradient power amplifier with gradient coil is proposed. Second, noise modeling with respect to the critical aspects in the system resolution degradation is developed and discussed. Third, the resolution improvement methods of bandwidth optimization, pseudorandom code modulation, and utilizing silicon carbide (SiC) switching power devices are proposed and analyzed, achieving a resolution at the one part in ${10^6}$ level. Finally, the resolution improvement methods are experimentally validated in a 1000 V/400 A SiC gradient power amplifier. The experimental results show a 3.6 times reduction in the peak spurious signals and resolution improvement at all current levels and pulse lengths, compared to a conventional insulated gate bipolar transistor GPA. These results prove the validity of the proposed methods for resolution improvement in a high-power MRI gradient power amplifier, enabling future high-power and high-resolution amplifier designs.

This work integrates a harmonic tuning mechanism in synergy with the GaN HEMT transistor for 5G mobile transceiver applications. Following a theoretical study on the operational behavior of the Class-F power amplifier (PA), a complete amplifier design procedure is described that includes the proposed Harmonic Control Circuits for the second and third harmonics and optimum loading conditions for phase shifting of the drain current and voltage waveforms. The performance improvement provided by the Class-F configuration is validated by comparing the experimental and simulated results. The designed 10W Class-F PA prototype provides a measured peak drain efficiency of 64.7% at 1dB compression point of the PA at 3.6 GHz frequency. Agencia Estatal de Investigación | Ref. TEC2017-88242-C3-2-R

In magnetic resonance imaging (MRI), high-power gradient power amplifiers (GPAs) are required to drive the gradient coils to generate strong and high-fidelity gradient fields. High precision is an essential requirement for the GPAs since precision directly impacts MRI imaging quality. Various aspects of the GPA have been the subject of research in the past years; however, high-precision GPA control that meets the stringent requirements of MRI applications is still a challenge. This article proposes a novel multi-rational-delay variables state space control method and an efficient out-of-band signal injection method to achieve GPA control accuracy at the level of one part per million at MVA output power levels. First, a systematic modeling and design method of the state space controller for high-power GPA is introduced utilizing state vectors with multi-rational-delay variables. This method improves the GPA dynamic performance significantly. Second, an efficient out-of-band signal injection method is presented to further improve the control precision at low output current, enabling the fulfillment of the challenging high-precision MRI requirements over the full GPA output range. Finally, the high-precision control method is validated in a GPA demonstrator with 500 A/1000 V output. Key results are a 30% improvement in current pulse reproducibility with respect to the conventional control method and a factor of 2.5 less noise at low currents. These experimental results validate the proposed novel method for the high-precision control of GPAs in MRI applications and prove its capability to contribute to significantly improved MRI image quality.

With the evolution of communication technology applications, wireless telecommunication systems are expected to be more and more robust and performance/cost effective. As per the market survey, data traffic is evolving with the technology applications and is expected to go up to 100s of Exabyte/month by 2030. To support such high data traffic, wireless transceivers are expected with larger bandwidth, high spectral and power efficiency support. On the digital back-ends of the wireless communication, modulations schemes become more and more complex to improve the data rates. However, in the wireless communication, quality of services (QoS) is majorly determined by the physical layer, especially by components such as power amplifiers. With considering this fact, in this dissertation, characterization of the active device through the load-pull process is studied for understanding the behavior of increased wideband scenario. Load-pull is performed with LDMOS and GaN technology using computer-aided design tool (CAD) such as advanced design system (ADS). Baseband impedance is also studied with the two-tone analysis to study the memory effect that causes the degradation in linearity and efficiency. Com a evolução das aplicações de tecnologias de comunicações, é esperado que os sistemas de telecomunicações sem fios sejam mais robustos e eficazes a nível de performance/custo. Conforme um inquérito de mercado, o tráfego de dados está a evoluir em conjunto com as aplicações de tecnologia e ´e esperado que em 2030 tenha aumentado até às centenas de Exabytes por mês. Para suportar quantidades de tráfego tão grandes, são esperados transrecetores com apoio para larguras de banda maiores, eficiência espectral e de potência. No processo digital interno das comunicações sem fios, os esquemas de modulação tornam-se mais complexos para melhorar a taxa de dados. Contudo, nas comunicações sem fios, a qualidade de serviços é maioritariamente determinada pela camada física, especialmente por componentes tais como os amplificadores de potência. Considerando este facto, nesta dissertação, a caracterização do dispositivo ativo através do processo de load-pull é estudada para o entendimento do comportamento no cenário de aumento de banda larga. Load-pull ´e realizado com tecnologia LDMOS e GaN com o uso de ferramentas de desenho assistido (CAD) tais como advanced design system (ADS). A impedância de banda base também é estudada com análise de dois tons para estudar o efeito de memória que causa degradação na linearidade e eficiência. Mestrado em Engenharia Eletrónica e Telecomunicações

In the last years, the Radio Frequency Integrated Circuit (RFIC) market has grown significantly, being part of an RFIC Innovation Cycle. Due to the two main application drivers of communication and sensing, the market is pushing to have circuits operating at higher and higher frequencies, making the role of millimeter wave (mmWave) devices more and more important. In this band, many applications such as mmWave 5G, automotive radars and imaging unfold. However, circuit design at such high frequencies brings new challenges that must be faced. One of the main challenges is the design for power amplifier (PA) stability. The need of high gain in operating frequencies together with the fact that PA designs are becoming more integrated, with higher density, more potential feedback loops, easier resonances due to smaller wavelengths and less accessibility after fabrication, results in an increased risk of instability. On top of that, very often, designs that appear to be stable in simulations are not in measurements. This thesis aims to study the stability of mmWave PAs, providing a set of techniques that can be used by PA designers during design and layout to analyze and improve the stability of the design. With that goal, an extensive review of literature covering the main stability verification techniques is presented, showing their advantages and drawbacks and outlining the use of pole-zero identification together with loop gain as the most rigorous and insightful techniques. A stability analysis framework based on MATLAB and combined with Keysight ADS is described. The framework includes parametric and multiple nodes simulation, identification of critical nodes, improvements in selection of order of transfer function and modifications for computational efficiency. The framework is tested with three different designs, showing the expected results. The framework, together with complementary techniques, is applied to the use case of a 28-GHz Gallium Nitride (GaN) multistage PA that showed to be unstable in measurements but stable in simulations. Multiple parametric analyses are performed including bias, neutralization, CGD and thermal sweeps at different nodes. From them, the instability of the design due to process variations associated with the neutralization capacitance (CN) in the driver stage is concluded. Moreover, techniques to stabilize the 28-GHz PA and applicable to other mmWave PA designs are proposed. Finally, further improvements in stability analysis based on parametric residue and bifurcation analysis are presented.

In this paper, we propose an efficient approach for optimizing the decomposed vector rotation (DVR) model for digital predistortion (DPD). The DVR model’s basis functions are constructed piecewise by dividing the input space into segments bounded by thresholds. This paper investigates how to set the thresholds optimally using an iterative approach based on the decomposition of the global optimization problem into a set of unimodal sub-problems so that a unidirectional minimization can be used to optimize the positions of thresholds. The proposed approach has been evaluated using measurements from a real power amplifier (PA). The experimental results illustrate the efficiency of the proposed optimization approach and show that the thresholds’ optimization improves linearization performances significantly compared to conventional DVR with uniform segmentation.

Power amplifiers (PAs) are widely used in RF broadcasting applications. However, they exhibit nonlinear behavior and deteriorate the quality of transmitted signals. Digital predistortion (DPD) is developed to linearize the distortion generated by PAs. Due to the contradiction between modeling precision and complexity, to reduce the complexity and ensure comparable performance, it is necessary to determine an appropriate or optimized structure before applying DPD. Heuristic method is a good method to solve such multivariate problems with a considerable large search domain. In this paper, a novel approach to determine the structure of DPD based on heuristic method is proposed, including the enhanced hill-climbing (EHC) with stronger global search ability and enhanced genetic algorithm (EGA). Ridge regression is introduced to ensure the correctness of the search direction. Besides, orthogonal matching pursuit is used to further reduce the basis number while keeping good performance. The validation of the proposed techniques on a Doherty PA using generalized memory polynomial (GMP) model demonstrates the capability to efficiently find the dimensions of an appropriate GMP model. As shown by the convergence curve and the final model performance, the model searched by the proposed method has satisfactory results, and achieves a good balance between complexity and performance.

We present a compact W-band power amplifier (PA) for automotive radar application in 65-nm CMOS technology. The circuit adopts a pseudo-differential push-pull configuration based on transformers (TFs) which offer highly efficient and flexible matching networks with minimized area occupancy. We have set the optimal output resistance close to 50 $\Omega $ , design guidelines in sizing active devices for each stage, and the corresponding transformers were presented for optimal power efficiency based on an analysis of surrounding matching networks. Working under a supply voltage of 1.3-V, the implemented 77GHz PA achieved a 3-dB gain bandwidth of 9-GHz (72.5–81.5 GHz), a peak gain of 22.4 dB, a saturated power ( $P_{sat}$ ) of 16.4 dBm, and a peak power-added efficiency (PAE) of 20.3%. The area for the core layout is only 0.05 mm2, which demonstrates the highest power density among the recently reported W-band CMOS PAs.

Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Their linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and nonswitching driver cells. Often, digital predistortion (DPD) is required to transmit higher-order modulation schemes. In this letter, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. An SCPA with these driver cells is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process which demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of -50 dB and an error vector magnitude (EVM) of -45.5 dB for 5-MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.

A simple and effective method for linearization of power amplifiers (PAs) is proposed. The method is based on the second harmonic injection into the input of the PA. The second harmonic is generated in a feedback path by taking the low-power transistors of a pseudo-differential pair amplifier to their nonlinear regime. The amplitude and phase of the second harmonics are controlled by tunable matching networks of the pseudo-differential pair which include trimmer capacitors. Using a theoretical analysis, we show that the proposed method is capable of canceling the third-order intermodulation signal at the PA output. As a proof of concept, a 10-W PA in a frequency band of 1.4 - 1.6 GHz is designed and linearized. By fabricating both the reference and linearized PAs and performing measurements under several conditions, it is experimentally demonstrated that applying the proposed scheme, thanks to its adjustability, highly linearizes the PA in a wide bandwidth and a wide range of output power.

In this study, we proposed a power amplifier structure with improved efficiency while securing high output power. First, the characteristics of the common-source and stack structures were investigated. In particular, the output power and output impedance characteristics of the stack structure were analyzed compared with the common-source structure. A common-source structure was applied to the driver stage to minimize dc power consumption, and a stack structure was applied to the power stage to ensure high output power. In order to verify the proposed structure, a Ku-band power amplifier was designed using the 65-nm RF CMOS process that provides nine metal layers. At the operating frequency of 15 GHz, saturation output power and maximum power-added efficiency were confirmed to be 22.1 dBm and 17.2%, respectively.

A comparative evaluation is provided in this paper regarding two design approaches for Ka-band Gallium Nitride Power Amplifiers. The first approach uses the standard electrical models provided by the foundry, while the alternative approach uses a custom model derived from in-house load-pull characterization. Both Power Amplifiers are designed to provide 30 dBm output power and 30% efficiency in the 31 - 35 GHz bandwidth. It is shown that the PA based on the custom model has a better PAE performance by about 4% and higher output power by 0.3 dB.

This paper focuses on the FPGA implementation of a slew-rate reduction (SR) shaping function for envelope tracking (ET) power amplifiers (PAs). The SR envelope has been proved effective to trade-off power efficiency and linearity in ET PA systems where the envelope tracking modulator (ETM) is bandwidth limited. However, the implementation issues need to be addressed when targeting high clock rates to cope with current 5G new radio wide-band signals. This paper shows the FPGA implementation of the SR envelope generation. We explore the use of high-level synthesis (HLS) for the SR envelope generation to evaluate the performance and resource usage of the hardware architecture. The HLS design is also compared with a hand-written hardware description language (HDL) version. An in-depth analysis shows strengths and limitations of the HLS design to meet the timing constraints when considering a throughput of 614.4 MSa/s. © 2022 IEEE.

©2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This letter presents a novel reconfigurable, high-efficiency class-F power amplifier (PA) structure, using a commercial GaN-HEMT, that achieves dual-band configuration not only at the fundamental frequency but also at the harmonics. With a proper harmonic tuning structure, the need for an extra filtering section is eliminated, resulting in a high dual-band efficiency with a reduced number of components and size. The reconfigurable structure uses commercial singlepole-double-throw (SPDT) and single-pole-single-throw (SPST) MEMS switches optimally placed on the stubs to select between 900 and 1800 MHz. The reconfigurable PA achieves a measured power-added efficiency (PAE) of 69.5% and a power gain of 13.6 dB while delivering an output power of 39.1 dBm at 900 MHz. At 1800 MHz, the amplifier achieves a PAE of 57.9%, a power gain of 10.5 dB, and an output power of 38.5 dBm.

International audience; This paper presents a general survey of digital predistortion (DPD) techniques with segmentation. A comparison of global DPD with two segmented approaches namely Vector-Switched DPD and Decomposed Vector Rotation DPD is presented with the support of experimentation on a strongly non-linear 3 ways Doherty PA. It shows the interest of both segmented approaches in terms of linearization performance, complexity and ease of implementation compared to the global DPD. The paper starts with some mathematical generalities on interpolation and splines. It focuses on segmented models derived from Volterra series even if the presented principles can also be applied to neural networks.

We report design guidelines for a transformer-based push-pull power amplifier (PA) with a systematic stability test carried out in the complex frequency domain. By detecting the right half-plane zeros of the impedance matrix's determinant, the common-mode (CM) instability in a differential PA were accurately estimated with the established frequencies from the analysis. In the stability test, the parasitic series coupling capacitance of the input transformer and the parasitic inductance from the gate (base) biasing line were identified as the two primary mechanisms of the CM instability in a transformer-based PA contingent on stability. Based on the analysis of the instability mechanisms, useful stabilization methods were proposed and discussed for a robust push-pull PA design with a well-balanced performance. An onboard transformer-based push-pull PA was implemented for the verification purpose, and the effects of parasitic inductance on the stability had been investigated. The simulated and measured results corresponded well with the proposed analysis.

This paper deals with designing a simple and efficient simultaneous inductive power and data transmission for transcutaneous Micro-system based on ASK modulation at 6,78 MHz industrial, scientific, and medical (ISM) band to avoid the tissue damage. The modified ASK modulator and inductive coupling link driven by efficient Class-E power amplifier with 94,5% efficiency and the coupling link of up to 78,29% of efficiency are introduced to transmit 500 Kbit/s of data with modulation index 12,5%, modulation rate 7,37%. The proposed design is simple, easy to implement and able to power the bio-implantable devices with DC V up to 5 V. The mathematical model is given and the system is designed and validated by professional OrCADPsPice 16,6 environment simulation using a standard AMS 0,35 μm MOS technology. In addition, for real-time simulation, the electronic workbench MULISIM 11 has been used to simulate the class-E power amplifier switching. This design is useful for cochlear implants, retinal implants and implantable micro-system stimulator.

Multi-band (MB) technology arises as a suitable solution to increase capacity within future 6G networks, while efficiently utilizing the already deployed optical fiber infrastructure. Indeed, the adoption of MB sliceable bandwidth/bit rate variable transceivers (S-BVTs) based on multi carrier modulation (MCM) enables transmission within multiple bands beyond C-band, providing sustainable capacity growth and hyper-scalability. Different slices/bands can be suitably activated in a pay-as-you grow approach according to the network demand and requirements. Additionally, the proposed MB S-BVT architecture also enables disaggregation and programmability by the adoption of an open software-defined networking (SDN) paradigm. A proof of concept of the proposed MB S-BVT is numerically and experimentally evaluated. Specifically, the transmission of 25 GHz signals/slices working at C-, L- and S-band is considered without any filtering and amplification stages. About 70 Gb/s capacity per slice/band is achieved in B2B configuration. The data rate decreases after 50.47 km, enabling maximum capacities per slice of 26.2 Gb/s (C-band) and 21 Gb/s (L- and S-bands). Additionally, the proposed MB S-BVT can be envisioned to serve different classes of services/applications over different network segments, prepared to support MB technology, thanks to the exploitation of differently performing slices/bands. © 1983-2012 IEEE.

This paper presents a transmitter IC with two identical signal paths, including base-band amplifier, up-converting mixer, and power amplifier (PA) stages. The design is focused on wide modulation bandwidth, and the use of a resonatorless small die-area class-D power amplifier at cm-wave frequencies. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.8 mm2. Operation over the 6–20 GHz range of carrier frequencies through the transmission of both continuous wave (CW) and wideband quadrature phase shift keying (QPSK) modulated signals were verified with measurements. Results with 20/40/100, and 400 MHz modulation bandwidths are presented, and for instance for a 20-MHz QPSK modulated input signal the measured adjacent channel leakage ratio (ACLR) of the transmitter is 28 dBc and error vector magnitude (EVM) is 5%. acceptedVersion

This paper is an expanded version from the 2021 IEEE RFIC Symposium, Atlanta, GA, USA, June 7-9, 2021; International audience; A high data-rate D-band transmitter module cointegrating a dual channel transmitter IC in 45 nm CMOS PDSOI technology and an antenna is presented. The proposed system-inpackage is based on an innovative channel bonding technique and is fabricated using a low-cost printed circuit board process. The IC consists of two up-conversion chains including on-chip millimeter-wave local oscillator generators. The emitted signal is composed of eight channels, each one having 2.16 GHz bandwidth, organized in two sets of 4 channels at the IF band (around 61.56 GHz) that are up-converted to two adjacent sub-bands centered at 148 GHz. Then, the two sub-band signals are combined off-chip using a substrate integrated waveguide diplexer and radiated by a patch antenna array realized on the same package. The output spans from 139.3 to 156.6 GHz. The total equivalent isotropic radiated power is 8.3 dBm. A 84.48 Gb/s data rate is achieved with 64 QAM. The module consumes 600 mW from a 1-V supply and occupies a compact area of 12×6 mm$^2$ .

Power amplifiers (PAs) are the most power-hungry components in base stations (BSs), and thus they significantly contribute to the overall energy consumption and power efficiency of cellular networks. Unfortunately, PAs need to operate close to their compression or saturation region in order to be power efficient, which heavily distorts the transmit signals and other users or systems operating in adjacent frequency bands. Since such distortions can significantly compromise the spectral efficiency of networks, digital predistortion (DPD) solutions are commonly adopted at transmitters (TXs) to compensate for the PA-induced distortions. DPD is a well established and known technology in the context of legacy narrowband transmitters with a few antennas, however, the fifth generation of mobile communications (5G) introduces a number of technical developments that require a top-to-bottom redesign of traditional digital predistorters. Particularly, massive multiple-input-multiple- output (mMIMO) is a technique that makes it possible to multiplex a large number of users in the spatial domain, so that more information can be squeezed into the already limited and congested electromagnetic spectrum. Furthermore, it allows a more efficient utilization of the radiated energy, by synthesising very-sharp beams that focus the electromagnetic waves in the directions of interest, while minimizing interference elsewhere. However, mMIMO, in its large variety of topologies, imposes many new challenges to the design and implementation of DPD solutions, which if not addressed properly, can seriously compromise the efficient utilization of PAs in these transmitter architectures, leading to increased carbon footprint, to increased costs for network operators, and to more complex BS designs. This thesis presents a number of contributions in the field of digital predistortion, particularly for large antenna array or mMIMO transmitters, to address some of the major challenges encountered in their linearization, so that spectral and energy-efficient transmitters can be utilized in the present and future generation of cellular networks. The first contribution of this thesis adds to the foundation of the fundamental understanding of the effective linearization of phased-array and hybrid MIMO transmitters. To that end, mathematical models of the radiated nonlinear distortion are derived, followed by developing efficient beam-based predistortion and learning principles under different beamforming configurations and propagation scenarios. Particularly, it is shown that the composite over-the-air (OTA) combined distortion in the main-beam(s) can be effectively minimized by means of one-dimensional digital predistorters. Closed-loop-based DPD structures are adopted, which are more resilient to hardware impairments in the observation receivers and to crosstalk, together with reduced complexity gradient-based adaptive algorithms. Spatial-domain analyses of the radiated distortions are provided, revealing the rationale behind the cancellation of nonlinear distortion for every particular scenario. Comprehensive numerical experiments are provided, substantiating the different concepts. The second contribution is the development of a number of more advanced digital predistortion techniques that allow the linearization of practical active mmWave phased-array transmitters subject to challenging impairments. These solutions particularly deal with the compensation of strong and beam-dependent nonlinearities, while favouring reduced complexity processing. To that end, a closed-loop decorrelation-based piece-wise DPD, a multi-beam oriented neural-network-based DPD, and reduced complexity frequency-domain DPD processing were proposed. Extensive radio-frequency (RF) measurements demonstrate that the different solutions can provide excellent linearization performance, while dealing with very challenging hardware impairments in an efficient manner. The third contribution of this thesis is the development of stream-/beam-level predistorters for fully-digital MIMO architectures. Different DPD structures are proposed to enable the linearization of such MIMO transmitters through a single and common predistorter. By doing so, the need for deploying a dedicated DPD per PA/antenna unit is avoided, thus allowing for reduced complexity linearization of the whole transmitter. Different solutions are proposed for single-carrier and orthogonal frequency division multiplexing (OFDM) based transmitters, with single-user and multi-user transmission. Overall, the proposed methods and results provide clear advancements in the DPD technology area, beyond the current state-of-the-art.

Motivated by increasing precision requirements for switched power amplifiers, this paper addresses the problem of model predictive control (MPC) design for discrete-time linear systems with a finite control set (FCS). Typically, existing solutions for FCS-MPC penalize the output tracking error and the control input rate of change, which can lead to arbitrary switching among the available discrete control inputs and unpredictable steady-state behavior. To improve the steady-state behavior of FCS-MPC, in this paper we design a cost function that penalizes the tracking error with respect to a state and input steady-state limit cycle. We prove that if a suitable terminal cost is added to the FCS-MPC algorithm convergence to the limit cycle is ensured. The developed methodology is validated in direct switching control of a power amplifier for high-precision motion systems, where it significantly improves the steady-state output current ripple.

This paper presents an envelope linearization technique to compensate for the nonlinear distortion of envelope tracking (ET) power amplifiers (PAs) for 5G new radio (NR) mobile terminals. The proposed envelope optimization (EOPT) method is agnostic of the nonlinear distortion generated in the envelope supply path and can compensate for the nonlinear distortion at the ET PA output without the need to monitor the output at the envelope tracking modulator (ETM). The linearization system in the envelope path is based on the envelope generalized memory polynomial (EGMP) behavioral model. Since the ETM output is not available, an iterative nonlinear least squares solution inspired in the deep deterministic policy gradient (DDPG) algorithm is proposed to extract the coefficients of the EGMP model. The EOPT method is validated on a system-on-chip (SoC) ET PA board designed for mobile terminal applications. Experimental results show the suitability of the proposed method to guarantee the linearity requirements (i.e., adjacent channel power ratio below -36 dBc) with 16.8% of power efficiency when operating the ET PA with 5G new radio test signals of 60 MHz bandwidth operating at 2.55 GHz (band 7). The linearization performance of the proposed EOPT method is comparable to the envelope leakage cancellation (ELC) approach (but saving the need for an analog to digital converter to monitor the ETM output), and can outperform a conventional I-Q digital predistorter based on the generalized memory polynomial (GMP) behavioral model. This research was funded by Huawei Technologies from July 2020 to August 2021; and supported in part by the project PID2020-113832RB-C21 funded by MCIN/AEI/10.13039/50110001103 and in part by the Government of Catalonia and the European Social Fund under Grant 2021-FI-B-137.