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The C/C++ compilation stack (Intermediate Representations (IR), compilation passes and backends) is encumbered by a steep learning curve, which we believe can be lowered by complementing it with approaches such as source-to-source compilation. Source-to-source compilation is a technology that is widely used and quite mature in certain programming environments, such as JavaScript, but that faces a low adoption rate in others. In the particular case of C and C++ some of the identified factors include the high complexity of the languages, increased difficulty in building and maintaining C/C++ parsers, or limitations on using source code as an intermediate representation. Additionally, new technologies such as Multi-Level Intermediate Representation (MLIR) have appeared as potential competitors to source-to-source compilers at this level. In this paper, we present what we have identified as current challenges of source-to-source compilation of C and C++, as well as what we consider to be opportunities and possible directions forward. We also present several examples, implemented on top of the Clava source-to-source compiler, that use some of these ideas and techniques to raise the abstraction level of compiler research on complex compiled languages such as C or C++. The examples include automatic parallelization of for loops, high-level synthesis optimisation, hardware/software partitioning with run-time decisions, and automatic insertion of inline assembly for fast prototyping of custom instructions., OASIcs, Vol. 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023), pages 2:1-2:15

This paper presents results of a study of the performance of several base classifiers for recognition of handwritten characters of the modern Latin alphabet. Base classification performance is further enhanced by utilizing Viterbi error correction by determining the Viterbi sequence. Hidden Markov Models (HMMs) models exploit relationships between letters within a word to determine the most likely sequence of characters. Four base classifiers are studied along with eight feature sets extracted from the handwritten dataset. The best classification performance after correction was 89.8%, and the average was 68.1%

This paper presents the design and post-layout characteristics of a differential capacitance based inertial accelerometer This includes a MEMS based mechanical sensing element and a CMOS charge amplifier, which is the first stage of a readout circuit. The mechanical sensor is designed according to the SOIMUMPs fabrication process technology, and the readout circuit targeted AMS 0.35um technology. Post layout simulations indicated a +/-5G dynamic range, a maximum bandwidth of 1.58 kHz, non-linearity of 0.077% and a resolution of 10.5 uG/Hz^0.5. The readout circuit charge amplifier is fully differential and incorporated in a switched capacitor (SC) topology with CDS.

With the ever more pressing issue arising from the phenomenon known as the death or slowdown of Moore’s Law and the Dennard Scaling, compute performance has not been increasing at the rate the industry had been accustomed to over the decades [7]. This has prompted a shift from mostly homogeneous compute architectures to increasingly heterogeneous ones [1]. As these systems become increasingly complex, manual tuning and management of these heterogeneous resources becomes unfeasible. In this paper, we propose a runtime mechanism for automatic reconfigurable resource management that will enable a hypothetical flow for combined hardware and software compilation.

High-Level Synthesis has introduced reconfigurable logic to a new world -- that of software development. The newest wave of HLS tools has been successful, and the future looks bright. But is HLS the end-all-be-all to FPGA acceleration? Is it enough to allow non-experts to program FPGAs successfully, even when dealing with troublesome data structures and complex control flows -- such as those often encountered in graph algorithms? We take a look at the panorama of adoption of HLS by the software community, focusing on graph analysis in particular in order to generalise to \textit{FPGA-unfriendly} problems. We argue for the existence of shortcomings in current HLS development flows which hinder adoption, and present our perspective on the path forward, including how these issues may be remedied via higher-level tooling., 3 pages, 1 table. Accepted at LATTE '21, an ASPLOS workshop. Slightly differs from accepted version: includes some corrections and phrasing changes

Decision trees are often preferred when implementing Machine Learning in embedded systems for their simplicity and scalability. Hoeffding Trees are a type of Decision Trees that take advantage of the Hoeffding Bound to allow them to learn patterns in data without having to continuously store the data samples for future reprocessing. This makes them especially suitable for deployment on embedded devices. In this work we highlight the features of an HLS implementation of the Hoeffding Tree. The implementation parameters include the feature size of the samples (D), the number of output classes (K), and the maximum number of nodes to which the tree is allowed to grow (Nd). We target a Xilinx MPSoC ZCU102, and evaluate: the design's resource requirements and clock frequency for different numbers of classes and feature size, the execution time on several synthetic datasets of varying sample sizes (N), number of output classes and the execution time and accuracy for two datasets from UCI. For a problem size of D3, K5, and N40000, a single decision tree operating at 103MHz is capable of 8.3x faster inference than the 1.2GHz ARM Cortex-A53 core. Compared to a reference implementation of the Hoeffding tree, we achieve comparable classification accuracy for the UCI datasets.

This paper presents results of a study of the performance of several base classifiers for recognition of handwritten characters of the modern Latin alphabet. Base classification performance is further enhanced by utilizing Viterbi error correction by determining the Viterbi sequence. Hidden Markov Models (HMMs) models exploit relationships between letters within a word to determine the most likely sequence of characters. Four base classifiers are studied along with eight feature sets extracted from the handwritten dataset. The best classification performance after correction was 89.8%, and the average was 68.1%

This paper presents and discusses an implementation of a multiple target tracking method, which is able to deal with target interactions and prevent tracker failures due to hijacking. The referenced approach uses a Markov Chain Monte Carlo (MCMC) sampling step to evaluate the filter and constructs an efficient proposal density to generate new samples. This density integrates target interaction terms based on Markov Random Fields (MRFs) generated per time step. The MRFs model the interactions between targets in an attempt to reduce tracking ambiguity that typical particle filters suffer from when tracking multiple targets. A test sequence of 662 grayscale frames containing 20 interacting ants in a confined space was used to test both the proposed approach and a set of importance sampling based independent particle filters, to establish a performance comparison. It is shown that the implemented approach of modeling target interactions using MRF successfully corrects many of the tracking errors made by the independent, interaction unaware, particle filters.

O presente relatório tem como objetivo apresentar uma reflexão crítica e projetiva sobre as práticas desenvolvidas no estágio pedagógico em Educação Física, realizado na Escola Secundária Braamcamp Freire, na Pontinha, durante o ano letivo 2016/2017. Para a concretização deste propósito formativo há que salientar as diferentes áreas de intervenção do estágio no modo como possibilitaram o crescimento profissional através da lecionação de aulas de Educação Física, do acompanhamento de um diretor de turma, da participação num núcleo de desporto escolar e da intervenção no contexto escolar através de um projeto de investigação-ação. Ao longo do relatório serão dados a conhecer os diferentes níveis de participação e intervenção expondo as maiores dificuldades sentidas e as estratégias utilizadas para superar cada situação, na certeza que cada momento vivenciado ao longo do ano letivo contribuiu de forma inequívoca para a formação do meu perfil docente. Este estágio pedagógico consolidou uma visão quanto ao papel que o professor deve ter, não apenas na gestão do processo de ensino-aprendizagem da sua disciplina, mas também em todo o processo educativo promovido pela comunidade escolar. Para tal é imprescindível encarar a formação inicial como um processo que tem o seu término, mas que deve representar um ponto de passagem face à necessidade que a carreira docente apresenta de estarmos em contante atualização de forma a potenciar o sucesso educativo dos alunos. The current report aims to presente a critical reflection on the pedagogical internship implemented in the Physical Education (PE) teacher training, that took place at the Secondary School of Braamcamp Freire, in Pontinha, during the academy year 2016/2017. Concerning the teacher training achievement, one most emphasise its core áreas and lay stress on the professional growth it enabled through the teaching os PE classes, the monitoring of the class along with the class director, the participation in a Sports School Centre and finally the intervention in the school context according to na investigation-action project applied. The report will expose diferente levels of participations and it will unveil the most significant difficulties and the strategies used to overcome them, However, it must be highlighted that each experience lived during this academic year has contributed undoubtedly to my formation as teacher. This pedagogical training consolidated not only the importance of the teacher’s role in the learning teaching process, but also in the educational process endorsed by the school community. Therefore, one must face basic training as na essential procedure. Nonetheless, one must also bear in mind that teaching requires constant pedagogical updates in order to promote the educational success of students.

Recent work has shown how chemical reaction network theory may be used to design dynamical systems that can be implemented biologically in nucleic acid-based chemistry. While this has allowed the construction of advanced open-loop circuitry based on cascaded DNA strand displacement (DSD) reactions, little progress has so far been made in developing the requisite theoretical machinery to inform the systematic design of feedback controllers in this context. Here, we develop a number of foundational theoretical results on the equilibria, stability, and dynamics of nucleic acid controllers. In particular, we show that the implementation of feedback controllers using DSD reactions introduces additional nonlinear dynamics, even in the case of purely linear designs, e.g. PI controllers. By decomposing the effects of these non-observable nonlinear dynamics, we show that, in general, the stability of the linear system design does not necessarily imply the stability of the underlying chemical network, which can be lost under experimental variability when feedback interconnections are introduced. We provide an in-depth theoretical analysis of an example illustrating this phenomenon, whereby the linear design does not capture the instability of the full nonlinear system implemented as a DSD reaction network, and we further confirm these results using VisualDSD, a bespoke software tool for simulating nucleic acid-based circuits. Our analysis highlight the many interesting and unique characteristics of this important new class of feedback control systems., Considerable extension with respect to the previous version: additional results on the equilibria and stability for this class of systems, and the simulation with DSD reactions are now carried the VisualDSD tool

É crescente a valorização da conversão do conhecimento fundamental desenvolvido pelos cientistas em produtos concretos, socialmente relevantes. No Laboratório de Fonética da Universidade de Lisboa tem-se trabalhado nos últimos anos tanto em domínios de investigação fundamental, como de investigação aplicada. Neste artigo é feita uma revisão dos principais recursos recentemente disponibilizados à comunidade por este Laboratório visando o acesso a informação sobre frequência fonológica e lexical. São sumariamente apresentados, em particular, as aplicações informáticas para extração de informação de frequência fonológica e lexical FreP (V2016) e FreLex, a base de dados alargada FrePOP (agora sobre um corpus de cerca de 2 milhões de palavras), e 3 novos léxicos, o FrePOP Lexicon (frequência lexical num corpus de 3 milhões de palavras), o PLEX5 – Um léxico Infantil para o Português Europeu e o CDS_EP – Frequência lexical nos dados de fala dirigida à criança da FrePOP (0;11 a 3;04 ). São ainda revistos estudos recentes que fizeram uso destes recursos, ilustrando a sua utilidade em domínios de investigação fundamental e aplicada.

Submitted by Manuel Moreno (manuelmoreno@campus.ul.pt) on 2017-01-19T11:48:43Z No. of bitstreams: 1 ulfl221664_tm.pdf: 2591088 bytes, checksum: 9005b2fb254a6c56fafe4085c4ed9389 (MD5) Made available in DSpace on 2017-01-19T11:48:54Z (GMT). No. of bitstreams: 1 ulfl221664_tm.pdf: 2591088 bytes, checksum: 9005b2fb254a6c56fafe4085c4ed9389 (MD5) Previous issue date: 2016

This paper describes the design and experimental evaluation of a multibit Sigma-Delta (ΣΔ) modulator (ΣΔM) with enhanced dynamic range (DR) through the use of nonlinear digital-to-analog converters (DACs) in the feedback paths. This nonlinearity imposes a trade-off between DR and distortion, which is well suited to the intended hearing aid application. The modulator proposed here uses a fully-differential self-biased amplifier and a 4-bit quantizer based on fully dynamic comparators employing MOS parametric pre-amplification to improve both energy and area efficiencies. A test chip was fabricated in a 130 nm digital CMOS technology, which includes the proposed modulator with nonlinear DACs and a modulator with conventional linear DACs, for comparison purposes. The measured results show that the ΣΔM using nonlinear DACs achieves an enhancement of the DR around 8.4 dB (to 91.4 dB). Power dissipation and silicon area are about the same for the two cases. The performance achieved is comparable to that of the best reported multibit ΣΔ ADCs, with the advantage of occupying less silicon area (7.5 times lower area when compared with the most energy efficient ΣΔM).

Submitted by Fátima Piedade (fpiedade@sa.isel.pt) on 2013-01-25T12:02:49Z No. of bitstreams: 1 A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage.rep.pdf: 197771 bytes, checksum: b84dff820d6e002b44d737c1ccd4460c (MD5) Made available in DSpace on 2013-01-25T12:02:49Z (GMT). No. of bitstreams: 1 A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage.rep.pdf: 197771 bytes, checksum: b84dff820d6e002b44d737c1ccd4460c (MD5) Previous issue date: 2012

Submitted by Fátima Piedade (fpiedade@sa.isel.pt) on 2013-01-25T12:44:19Z No. of bitstreams: 1 A Step-up mu-Power Converter for Solar Energy Harvesting Applications, using Hill Climbing MaximumPower Point Tracking.rep.pdf: 193211 bytes, checksum: 42725df66b42b6fdab94f8df94fe923a (MD5) Made available in DSpace on 2013-01-25T12:44:19Z (GMT). No. of bitstreams: 1 A Step-up mu-Power Converter for Solar Energy Harvesting Applications, using Hill Climbing MaximumPower Point Tracking.rep.pdf: 193211 bytes, checksum: 42725df66b42b6fdab94f8df94fe923a (MD5) Previous issue date: 2011

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Telecomunicações. Universidade do Porto. Faculdade de Engenharia. 2011

Reliable biochemical implementations of linear controllers can provide a large set of tools for the design and analysis of control in Synthetic Biology. Theoretical frameworks are now available to represent feedback control systems as chemical reaction networks which can be readily translated into equivalent nucleic acid-based chemistry. However, the development of tools for constructing and analysing such controllers is still in its infancy.\ud \ud \ud Nucleic acid-based chemistry is a strong candidate framework for the construction of future synthetic biomolecular control circuits. The capacity of strand displacement reactions with Deoxyribonucleic Acid (DNA) to implement analogue signal processing in vitro and in vivo makes them a promising candidate to embed synthetic feedback control circuitry in biomolecular environments. However, little progress has so far been made in developing the requisite theoretical machinery to inform the systematic design of feedback controllers in this context. \ud \ud Here, the potential complexity of such controllers is extended significantly by showing how time-delays, numerical differentiation (to allow proportional-integral-derivative control), and state feedback may be implemented via chemical reaction network-based designs.\ud \ud \ud This work also provides a number of foundational theoretical results on the equilibria, stability, and dynamics of nucleic acid controllers, and the analysis highlights the many interesting and unique characteristics of this important new class of feedback control systems. In particular, that the implementation of feedback controllers using DNA strand displacement reactions introduces additional nonlinear dynamics, even in the case of purely linear control designs, and a robust design of the linear system does not imply the robustness of its chemical implementation.\ud \ud \ud The robustness of the controllers to experimental uncertainty is analysed with the structured singular value (µ) analysis tool, which is extended with a model of how parametric uncertainty in the system affects the location of its equilibrium. This framework provides more reliable results than sampled based statistical methods, where analysis via Monte Carlo simulation fails to uncover the worst-case uncertainty combination found by µ-analysis.\ud \ud The implementations of the examples and controllers in nucleic acid-based chemistry are simulated and checked using the Visual DSD simulation package, a bespoke software tool for simulating nucleic acid-based circuits.\ud

Esta dissertação consiste inicialmente na realização de uma revisão geral a vários tipos de Moduladores Sigma-Delta implementados de diferentes formas e utilizando várias estratégias diferentes que possibilitam a sua decimação. Foi também realizada a análise mais detalhada ao modulador Sigma-Delta Incremental, tendo sido implementado um modulador de primeira ordem e um modulador de Segunda ordem que foram filtrados com o filtro CoI (Cascata de Integradores) e um filtro que se baseia num algoritmo de decodificação ótimo. Para as arquiteturas que foram desenvolvidas e analisadas detalhadamente, foi obser- vado em simulações no software Octave os valores das métricas SNDR e DR de modo a otimizar as arquiteturas. Com esta análise concluiu-se que, para aplicação em sistemas reais, tanto para os moduladores primeira ordem como para os moduladores de segunda ordem, nenhum dos casos analisados (com filtro CoI e com filtro ótimo) tem uma grande vantagem perante o outro, ainda assim o filtro ótimo obtém valores ligeiramente supe- riores. This dissertation initially consists of a general review of several types of Sigma-Delta Mo- dulators implemented in different ways and using several different strategies that enable their decimation. A more detailed analysis of the Sigma-Delta Incremental modulator was also carried out, having implemented a first-order modulator and a second-order modulator which were filtered with the CoI filter (Cascade of Integrators) and a filter based on an algorithm optimal decoding. For the architectures that were developed and analyzed in detail, the values of the SNDR and DR metrics were observed in simulations in Octave software, to optimize the ar- chitectures. With this analysis it was concluded that, for application in real systems, both for the first order modulators and for the second order modulators, none of the analyzed cases (with CoI filter and with optimal filter) has a great advantage over the other, the optimal filter still gets slightly higher values.

This work contains an analysis of multiple topologies of DC-DC voltage buck con verters. The main goal of this Thesis is to study and design a functioning Step Down converter for capacitive coupling devices used for energy harvesting from the power AC grid. In order to achieve this goal, multiple topologies and circuits of this type of converter are studied and analysed, so that the requirements for the intended application are met. Since the input is obtained from the AC power grid and the output is connected to a supercapacitor, this results in a large input voltage (over 150V) and a low output voltage (between 1V to 3V), therefore the converter requires a step down voltage conversion ratio of around 130. The DC-DC converter should also have a large input impedance (around 50Mohm) to maximize the energy transferred from the power grid. This mode of operation is not common for regular inductance based DC-DC converters, making this a challenging problem. Moreover, since the amount of energy available from the capacitive coupling is very small, it is also necessary to develop a controller circuit that is capable of created a clock with a very low duty cycle while dissipating less than 50uW. Este trabalho visa analisar várias tipologias de conversores de tensão DC-DC deno minados conversores Buck. O principal objectivo desta Tese é estudar e projectar um conversor DC-DC abaixador de tensão para sistemas de acopelamento electromagnético capacitivo utilizada em aplicações de Energy Harvesting a partir da rede AC. De forma a cumprir este objectivo, várias tipologias são estudadas ao longo deste trabalho, de forma a cumprir as especificações exigidas. Uma vez que o sinal de entrada é obtido a partir da rede AC, e que o output está ligado a um supercondensador, isto faz com que a tensão de entrada seja elevado (Acima dos 150V) e a tensão de saída seja baixa (entre 1V e 3V), como tal o conversor precisa de um rácio de abaixamento bastante elevado de cerca de 130 vezes. O conversor DC-DC deve também ter uma impedância de entrada elevada (cerca de 50MOhm) por forma a maximizar a energia transferida da rede de energia. Estas condições de funcionamento não são habituais para conversores DC-DC indutivos, o que torna este um problema muito desafiante. Adicionalmente, uma vez que a energia disponivel devido ao acopelamento capacitivo é muito reduzida, é necessário desenvolver um circuito controlador capaz gerar um sinal de relógio com um duty cycle reduzido enquanto dissipa menos de 50uW de potência.

In recent years, there has been a breakthrough in integrated circuit technology, which has enabled the full integration of systems on a single chip and the development of increas ingly compact and low-power devices, such as IoT devices and smart devices. Usually, these devices come equipped with sensors and transceivers that make the interaction between the analog world and the digital world. In some of these devices Delta-Sigma modeling ( ∆Σ) is used to make the conversion from analogue to digital (ADC). In addition, the linear voltage regulator Low Dropout (LDO) is commonly used as the reference voltage buffer for the ADC ∆Σ. Since it is intended to do full system integra tion on a chip it is necessary to perform LDO integration. However, the LDO usually requires an external capacitor on the order of micro Farads to ensure stability, which makes integration of this circuit impossible. Currently, there are studies of LDO that do not need an external capacitor to be integrated into a chip. Among the proposals analyzed, it was found that some LDO are designed to have fast transient response and others, high PSRR. However, designing an LDO with these characteristics comes with new challenges such as ensuring stability, preventing PSRR degradation, and ensuring the speed of the transient response without causing an increase in the power consumed by the LDO. Traditionally, between the LDO and the ADC there is a switch switching very quickly, knowing the switching interval of the switch. Thus, in the present study a new architec ture is presented, based on the traditional LDO, but with a Miller compensation circuit that adapts to the load current. This compensation circuit allows to guarantee the sta bility and transient response of the circuit in each state of the current in the load. The developed LDO can achieve a gain of 77.3 dB, the PSRR at frequency of 1 kHz is 78.72 dB, when the IL = 20 .T hecurrentconsumedbytheLDOis IQ = 49.69 microA and when the switch between the LDO and the ADC is turned on, the IL transitions from 0 Ato20 milliA and takes 77.71 nanos until it stabilizes and provides a stable voltage to the ADC. Nos últimos anos, tem se verificado um avanço na tecnologia dos circuitos integrados, que tem permitido fazer a integração total de sistemas num único chip e o desenvolvimento de dispositivos cada vez mais compactos e de baixa potência, como os dispositivos IoT e smart devices. Normalmente estes dispositivos vêm equipados com sensores e transcetores que fazem a interação entre o mundo analógico e mundo digital. Em alguns destes dispositivos é utilizada a modelação Delta-Sigma ( ∆Σ) para fazer a conversão do analógico para o digital (ADC). Para além disso, é comummente usado o regulador de tensão linear Low Dropout (LDO) como buffer de tensão de referência para o ADC ∆Σ. Como se pretende fazer a integração total do sistema num chip é necessário realizar a integração do LDO. Contudo, o LDO normalmente necessita de um condensador externo na ordem dos micro Farads para assegurar a estabilidade, o que impossibilita a integração deste circuito. Atualmente, existem estudos de LDO que não precisa de ter um condensador externo para se realizar a integração deste, num chip. Entre as propostas analisadas verificou-se que alguns LDO são desenvolvidos por forma a ter rápida resposta transitória e outros, elevado PSRR. Contudo, projetar um LDO com essas características vem com novos desafios como assegurar a estabilidade, prevenir a degradação do PSRR, e garantir a velocidade da resposta transitória sem causar o aumento da potência consumida pelo LDO. Tradicionalmente, entre o LDO e o ADC há um interruptor a comutar muito rapidamente, conhecendo-se o intervalo de comutação do interruptor. Desta forma, no presente estudo é apresentada uma nova arquitetura, baseada no LDO tradicional, mas com um circuito de compensação de Miller que se adapta à corrente da carga. Este circuito de compensação permite garantir a estabilidade e a resposta transitória do circuito em cada estado da corrente na carga. O LDO desenvolvido consegue atingir um ganho de 77,3 dB, o PSRR a frequência de 1 kHz é 78,72 dB, quando o IL = 20 mA. A corrente consumida pelo LDO é IQ = 49,69 µA e quando o interruptor entre o LDO e o ADC é ligado, o IL transita de 0A para 20 mA e demora 77,71 ns até estabilizar e fornecer uma tensão estável ao ADC.

O ADC de Registo de Aproximações Sucessivas (SAR) apresenta diversas vantagens face a outros conversores, nomeadamente, uma área reduzida, um baixo consumo de energia e pode ser utilizado para resoluções mais altas com uma velocidade de conversão moderada, pelo que é diversas vezes utilizado para redes de sensores sem fios e produtos biomédicos. Este tipo de Conversor Analógico-Digital beneficia, assim,do avanço tecnológico.O principal objetivo desta dissertação é o estudo de um SAR ADC com Conversor Digital-Analógico C-2C. Este tipo de arquitetura é pouco utilizada para conversores do tipo SAR daí que o DAC usualmente utilizado entre os autores é o DAC Pesado Binariamente. Contudo,o DAC C-2C apesar de ser pouco conhecido e utilizado apresenta as suas vantagens em relação ao DAC Pesado Binariamente.Inicialmente, o DAC C-2C é alvo de um estudo teórico no domínio da tensão, tendo como finalidade o desenvolvimento de um modelo de alto nível a partir do simulador MATLAB, o que permitiu resultados ao nível do processo de conversão do ADC para diferentes cenários e o estudo do ponto de vista da linearidade e de eficiência energética.Por fim,e perante diferentes tópicos de estudo é elaborada uma análise comparativa entre os dois DACs mencionados anteriormente. Este estudo permitiu verificar que o DAC C-2C apresenta vantagens em relação ao DAC Pesado Binariamente, nomeadamente ao nível da área e eficiência energética. The ADC of Successive Approximation Register (SAR) has several advantages over other converters namely, a reduced area, a low power consumption, and can be used for higher resolutions with a moderate conversion speed so it is often used for wireless sensor networks and biomedical products. This type of Analog-to-Digital Converter thus benefits from technological advancement.The main objective of this dissertation is the study of a SAR ADC with C-2C Digital -to -Analog Converter. This type of architecture is seldom used for converters of the SAR type, hence the DAC usually used among authors is the Binary Weighted DAC. However, C-2C DAC despite being little known and used has its advantages over Binary Weighted DAC.Initially, the DAC C-2C is the target of a theoretical study in the voltage domain, with the purpose of developing a high level model from the MATLAB simulator, which allowed results at the level of the ADC conversion process for different sce-narios and the study from the point of view of linearity and energy efficiency.Finally, and in view of different study topics, a comparative analysis is made between the two DAGs mentioned above. This study allowed us to verify that the DAC C-2C has advantages over the Binary Weighted DAC, namely in terms of area and energy efficiency.

This thesis addresses the problem of voice recognition, by studying how to build a lowcost solution for data acquisition, presents the analysis, design implementation and simulation of a low-cost continuous-time(CT) passive sigma-delta modulator(SDM) with signal-to-noise-plus-distortion ratio(SNDR) > 86dB to increase fidelity in voice recognition applications. Employing passive RC integrators and a differential signal structure, the CT passive SDM is optimized to work as independently from a specific comparator module as possible, by decreasing the necessary gain of the comparator in the modulator gain. Nevertheless, the loop gain is restricted by the comparator’s noise, aggravated by the high attenuation of the passive RC integrators on the signal, causing low voltage swing at the comparator’s input. It is discussed the viability of utilizing a microprocessor (μP) as substitute of the comparator block in a CT passive SDM, specifically, the esp32. Due to hardware limitations and the high-frequency requirements of the CT passive SDM, it is proven this substitution is not viable. Along the course of the design implementation a comparison in the performance of three different simulation software is presented, these software being, the open-source LTspice VII, the open-source Ngspice and the private Cadence Virtuoso. As it was necessary to change simulation software at different stages in the design of the circuit.

In analog to digital conversion, it’s necessary to provide a reference voltage to the Analog to Digital Converter (ADC), in order to quantify the input signal. However, as the ADC has a switch constantly commuting on its input it will cause perturbations on the reference voltage provided by the Bandgap circuit. Thus, it will interfere with the normal behaviour of the Bandgap circuit, which will longer be capable of provide the desired reference voltage. Besides, if the reference voltage is not constant in the desired value the output code generated by the ADC will have errors. In order to avoid conversion errors it will be needed to introduce a buffer between the Bandgap and the ADC. Thus, taking advantage from the characteristics of the buffer (low output impedance, high input impedance and unitary gain) the system will be capable of recover from the perturbations introduced by the ADC in the reference voltage. Therefore, in this thesis are studied some of the already existing architectures of buffers, in order to see the advantages and disadvantages of each one. This way were chosen the best three architectures from a theoretical point of view, to implement and simulate, to obtain all the needed information in order to better compare them.

The occurrence of wildfires is a matter of preoccupation, specially in Portugal. In those disasters, many fire fighters are deployed to try put out the flames. However, when driving to the fire or away from it, the vehicles carrying the fire fighters might be in a dangerous situation, whether it is from being surrounded by flames or because of a drop in the levels of oxygen. The aftermath of the wildfires is also a focal point, since it’s hard for the fire fighters to verify its perimeter looking for possible reignition points. To overcome these problems, two modules were created. The first behaves like an alarm for fire fighting vehicles, verifying the surrounding temperatures and the oxygen levels inside the vehicle. If the vehicle is found in a dangerous situation, a message of emergency is sent to a central server, with the coordinates of the vehicle and the type of danger, in order to someone send help. The second module works like a scanner installed in a vehicle, collecting an array of temperatures in different positions, to analyse the perimeter of the wildfire and detect possible reignition points. This project will help central communication stations to acknowledge the safety state of fire fighting vehicles, as well as to have a more efficient aftermath analysis of wildfires.

A presente dissertação propõe o desenvolvimento de um sistema eletrónico de aquecimento para sous vide. Sous vide é um método de cozinhar a temperaturas precisas e baixas num longo período de tempo, permitindo realçar o sabor e a nutrição de um alimento. Atualmente, a presença de tecnologia numa cozinha é uma realidade, havendo uma constante evolução e cada vez mais, maior ligação entre estas. Uma das características do uso de tecnologia nas cozinhas modernas é a facilidade com que hoje em dia é possível alcançar melhores resultados no que toca à confeção de receitas, destacando-se o uso de robôs e equipamentos que executam ou facilitam a realização de determinadas tarefas exigidas pelas mesmas. Efetivamente quando se trata da cocção de um alimento, a temperatura e o tempo são fatores importantes, estando o nível de cozedura dependente dessas medidas. Desta forma, um controlo sobre a temperatura e o tempo resultará num controlo sobre a cozedura do alimento. Assim esta dissertação foca o desenvolvimento de um projeto que visa cumprir os requisitos para auxiliar a prática do método sous vide. Ao longo do documento apresenta-se o estudo e os trabalhos tomados a cabo para construção de um sistema apto a aquecer água, e adquirir informa-ção sobre a temperatura da mesma, processando-a de forma a contribuir para um controlo de tem-peratura da água.

Hoje em dia, cada vez mais o Homem beneficia da evolução tecnológica, sendo que os sistemas de aquisição de dados têm acompanhado muito essa evolução, posicionando-se na linha da frente para contribuir para a melhoria de diversas áreas da sociedade, com especial ênfase na saúde. Esta dissertação tem por objetivo desenvolver um sistema de aquisição de dados para sinais eletromiográficos, com vista à implementação de um rato para computador, controlado por este mesmo tipo de sinais biomédicos. Primeiramente, fez-se uma revisão bibliográfica de métodos, técnicas e de projetos já desenvolvidos, com caraterísticas semelhantes ao trabalho aqui proposto. Seguiu-se o escrutínio, das características dos sinais musculares e, posteriormente, uma análise dos vários processos de condicionamento, processamento e classificação do sinal, bem como modelos de aplicação existentes. Os conhecimentos adquiridos permitiram, depois, realizar uma fase de testes, com análise de resultados, em que se desenvolveram vários ensaios distintos, no que diz respeito à captação do sinal, bem como ao circuito de amplificação e ao processamento realizado, quer em Matlab, quer em PSoC. A última etapa diz respeito à implementação do rato para computador, apresentando, essencialmente, a montagem realizada no PSoC e os passos referentes à programação e à configuração das várias componentes utilizadas, para comandar este periférico através de sinais musculares.

In the current digital age, electronic devices are becoming increasingly more critical, especially mobile devices and "always-listening" devices such as virtual personal assistants. To gather data from the real world, which in this case is voice audio, digital devices need to convert the analog input signals captured by a microphone to a digital stream. The process of data conversion is usually an energy expensive process, where lower power drawing implementations would benefit battery powered devices and provide less energy consuming "always-listening" devices. One of the most appealing Analog to Digital Converter (ADC) implementations are done using Sigma-Delta Modulators ( Ms) due to their use of oversampling that allows the noise to be transferred to higher frequencies that can be posteriorly eliminated by a decimation filter. In discrete time Ms, implemented with Switched-Capacitor (SC), the full capacitor charging consumes a considerable amount of power; to improve this aspect, a partial capacitor charge could be implemented, allowing less energy to be used in each clock cycle. In this thesis, a Multi-stAge Noise SHaping (MASH) 2+1 M is implemented with Metal-Insulator-Metal (MIM) capacitors and Unsilicided P+ Polysilicon resistors with a sampling frequency of 10 MHz and a bandwidth of 20 kHz, to evaluate the practical feasibility of the architecture. Due to the expected decrease in performance when compared to the original circuit, the Mis improved and stabilized through the temperature range. The finalized MASH 2+1 M achieves 86.755 dB of Signal-to-Noise-and-Distortion Ratio (SNDR) with 2 kHz, 300 mV input signal while using an active silicon area of 96439.127 μm2 or around 0.0964 mm2 (this active area does not contain the Digital Cancellation Logic (DCL) circuitry).

This research work explores the relationship of Art and Science from the concept of Uncertainty. Uncertainty is the source of inspiration that drove the author to embark on a journey of discovery within two rather unknown fields to him, Glass and Electricity. The analogy made in this thesis between Glass and Electricity and Art and Science is a personal search for understanding the nature of the world, a dive into both the certainty of rational experimentation in the Scientific method, and the innate uncertain nature of experimentation in Art-making. This work is in essence a mirror that reflects the nature of the author’s mind, making visible some interesting ideas, impossible dreams, failed attempts and small discoveries. But above all, it’s a story of personal resilience, the search for a meaningful ‘ground’ and the ‘connection’ between Art and Science. In terms of practical goal, this study begins with fundamental considerations about how to achieve a new working method for Glass Printing formed from raw materials using controlled electric discharges.

Nowadays, electronic devices are ubiquitous. This spread across all scientific fields has allowed for greater development of solutions for problems once thought impossible, or impractical, to solve. Most specifically, it leads to a constant cost reduction in previously expensive technology, to a point where university students can acquire these devices and tinker with them, even finding applications that were not initially thought for the device. As a result, we began the development of this e-nose system, since it became increasingly important to know and understand the constituents and source of a chemical sample. This dissertation arises from the need to integrate the computational power inherent to a low-cost microcontroller unit, to identify chemical substances and their characteristics. With the main goal set, it was possible to formulate the guidelines to achieve a successful data acquisition channel for an e-nose system implementation with reduced costs, size and fast execution. The starting point consisted in understanding how previous implementations of this system work, as well as its most basic components. After researching and studying e-nose technologies, I was able to define two separate segments for a data acquisition channel: acquisition & communication module (hardware) and a data pre-processing module (software). By using a conductive polymer sensor with a PSoC 5LP microcontroller unit, it was possible to detect changes in the sensor response according to the chemical sample being tested, acquire this signal with the Delta Sigma ADC and, straight away, send this data to the computer where it would be pre-processed. This stage was implemented in Python and with its extensive signal processing libraries. Its main goal was to receive and store the data so that it could be use on a future pattern recognition algorithm to reach the final e-nose conclusion. Since this displayed to the user, a GUI was developed, and the resulting acquisitions could be displayed in several plots, as a way of verifying a successful operation. In the end, it was a success, since after performing acquisition, communication and displaying the results, subtle differences were visible on the plots displayed.

The HEP experiments that take place at CERN’s LHC demand a multi-gigabit optical link for an efficient transmission of the resulting generated data. An optoelectronic link arises as the best solution given its possibility of working at high data rates and due to fiber’s imunnity to electromagnetic noise. The design of this optical link is particularly demanding due to the stringent data rate specifications (5Gb/s), the BER specification (10􀀀12) and the constraints imposed by radiation. In HEP, radiation is always a constraint so, the Optical Receiver circuit must be hardened in order to tolerate that kind of environment - radiation-tolerant. The core of a standard optoeletronic receiver includes a Photodiode, a Transimpedance Amplifier (TIA) and a Limiting Amplifier (LA). This thesis proposes the study and implementation of one of these blocks (LA), as the main focus, as well as the analysis and design of all three other blocks. The two major design constraints regarding the LA are the bandwidth and minimising its power consumption, which were overcome by using two bandwidth enhancement techniques. The circuit yields a bandwidth of 4:8GHz with a power consumption under 19mW. Another fundamental block is the Output Buffer. The major request for this block was maintaining relatively low transition times and improving the signal’s integrity. It has a differential output swing around 400mV with Pre-emphasis levels larger than 130%. The third block is the Received Signal Strength Indicator (RSSI). From a system point of view it is useful to have a measure of the input signal’s power so that the communication channel is used in its full potential. With a power consumption smaller than 600μW the RSSI presents an input dynamic range larger than 50 dB. The fourth block implements a Squelch function, in order to suppress unwanted output toggling due to noise. All these elements were developed in a TSMC 65nm CMOS process with a 1:2V supply voltage.

In this Thesis, energy and area efficient techniques are discussed and a CT SDM, with 27.5 fJ/conv.-step of energy efficiency, employing passive RC integrators is presented. Between each passive RC integrator a simple differential pair is added, as low-gain open-loop amplifier, and most of the loop gain is obtained in the 1-bit comparator. Nevertheless, the processing gain is limited by the comparator’s noise due to the low voltage swing at the input of this building block. In order to maximize the performance, and due to a large number of trade-offs, such as the nonlinear behavior of the 1-bit quantizer that drastically affects the NTF (specially with low input signals), the circuit has been designed with a systematic design methodology, also proposed in this thesis based on a genetic algorithm (GA). Moreover, and due to the trade-off between RC variations and loop stability, the modulator is also optimized taking this undesired behavior in consideration, avoiding the need for any self-calibration. The 65 nm CMOS SDM prototype designed, implemented and experimentally evaluated during this research work, occupies only 0.013 mm2, dissipates 256 mWfrom a 0.7 V supply, and it achieves a peak SNDR of 69.1 dB in a 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a Schreier figure-of-merit (FoMSchreier) of 175.1 dB. To the best of the author’s knowledge, the proposed modulator is the most energy- and area-efficient designs published thus far1, considering SDMs with BWs larger than 50 kHz published at the two flagship conferences requiring silicon demonstration, namely, IEEE ISSCC and IEEE Symposium on VLSI Circuits [1].

Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters. In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process. This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms. The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time. Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB.

In today’s world, technology is so developed that it is possible to transmit huge amounts of data in a short time. In the experiments with high energy levels in laboratories carried out in CERN, it is essential to have a method capable of carrying all this information and at the same time of being tolerant to the radiation from these same experiments. Optical fibres are currently the best method transmitting the data created by these experiments. In order to receive the information from the optical fibre a Photodiode (PD) is used to produce current from the light of the optical fibre. This current is however small. It is necessary to use an amplifier which, in addition to amplifying the current coming from the photodiode, also converts it into a voltage for the next phases of the optical receiver. These amplifiers are known as transimpedance amplifiers and are the critical part of optical receivers since an high gain is required to amplify the current from the photodiode and at the same time a high bandwidth to receive the hight data rate signals. This thesis presents a complete analysis of these amplifiers, showing various types of topologies and their pros and cons. In order to arrive at the amplifier with the desired characteristics, this thesis uses mathematical equations that allow us to describe the operation of the Transimpedance Amplifier (TIA) and to determine the optimal range between the gain, the bandwidth and the noise of the amplifier (input referred noise). All the theoretical expressions as well as the behaviour of the whole system was verified using electrical simulations.

The demand for low power systems has been increasing in recent years and Analogto- Digital Converters (ADCs) are key blocks of many of these systems as they convert a physical quantity into the digital domain so that this information can be further processed or stored using digital techniques. Data Converters based on Charge Redistribution using of Successive Approximation Registers (SAR) are becoming one of the most popular ADC architectures for moderate speed, medium resolution and low power applications. Due to their low analog complexity SAR ADCs benefit from technology scaling. However, this scaling often comes with a supply voltage reduction and the noise levels do not decrease at the same rate, which translates into a performance decrease. Therefore, new opportunities emerge to explore other physical quantities such as time, frequency, phase or charge in the circuit. This thesis focuses on studying how the time domain information can be used to increase the performance of SAR ADCs. To do so, a new SAR ADC architecture is proposed in which a Time-to-Digital Converter (TDC) is used to convert the time domain information, provided by the comparator, into the digital domain. This new architecture was modelled in MATLAB as a 12 bit TDC assisted SAR ADC, using information from electrical simulations of the comparator and the TDC, designed in Cadence in 65 nm ST Microelectronics CMOS technology. Simulation results demonstrated that, to achieve a better performance when compared to more traditional SAR structures, the TDC energy and latency should be minimized. Another limiting factor was the large voltage range in which only 1 bit could be extracted from the time-to-voltage conversion by the TDC due to the comparator’s fast response in this range. The proposed architecture was also extended to incorporate a Bypass Window in the time domain, which allowed to substantially decrease the number of clock cycles necessary to solve the 12 bits of the ADC.

An energy harvesting system requires an energy storing device to store the energy retrieved from the surrounding environment. This can either be a rechargeable battery or a supercapcitor. Due to the limited lifetime of rechargeable batteries, they need to be periodically replaced. Therefore, a supercapacitor, which has ideally a limitless number of charge/discharge cycles can be used to store the energy; however, a voltage regulator is required to obtain a constant output voltage as the supercapacitor discharges. This can be implemented by a Switched-Capacitor DC-DC converter which allows a complete integration in CMOS technology, although it requires several topologies in order to obtain a high efficiency. This thesis presents the complete analysis of four different topologies in order to determine expressions that allow to design and determine the optimum input voltage ranges for each topology. To better understand the parasitic effects, the implementation of the capacitors and the non-ideal effect of the switches, in 130 nm technology, were carefully studied. With these two analysis a multi-ratio SC DC-DC converter was designed with an output power of 2 mW, maximum efficiency of 77%, and a maximum output ripple, in the steady state, of 23 mV; for an input voltage swing of 2.3 V to 0.85 V. This proposed converter has four operation states that perform the conversion ratios of 1/2, 2/3, 1/1 and 3/2 and its clock frequency is automatically adjusted to produce a stable output voltage of 1 V. These features are implemented through two distinct controller circuits that use asynchronous time machines (ASM) to dynamically adjust the clock frequency and to select the active state of the converter. All the theoretical expressions as well as the behaviour of the whole system was verified using electrical simulations.

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e Computadores The objective of this thesis is to study the behaviour of a bandgap voltage reference and develop it in order to be more efficient than the existing ones. In this case having applicability in energy harvest, the main approach for this circuit is to reduce the power dissipation and at the same time guarantee a stable of the reference voltage. This can be achieved through the utilization of MOS transistors which can work with a lower voltage then bipolar transistors. The reference voltage circuit present in this thesis can work with a supply voltage as low as 500 mV. In energy harvest systems besides the need to work with extremely low voltages, the sensitivity of the signals is very high, to temperature variation. So it was also important to work with an extended ranges of temperature. For this work it was also developed a temperature sensor so that it has applicability in various fields. The sensor works by currents generated by the bandgap voltage reference, having similar results to a dual slope integrating analogue-to-digital converter, although its operation and logic are quite different. The proposed solution is to implement a reference voltage generator powered by a voltage source of 500 mV, with a consumption of about 7 W. Having a temperature coefficient slightly below 74 ppm/ C and a temperature sensor with linearity quite satisfactory.

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Dissertação apresentada para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores