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There are various kinds of data sorting methods that we know of which are the Bubble Sort, Selection Sort, Insertion Sort, Quick Sort, Shell Sort, Heap Sort, and Radix Sort methods. All of these methods have advantages and disadvantages of each, whose use is determined based on needs. Each method has a different algorithm, where different algorithms affect the execution time. One interesting algorithm to be implemented on 2 variant models of data sorting is the Bubble Sort algorithm, the reason is that this algorithm has a fairly long and detailed process flow to produce an ordered data sequence from a previously unordered data sequence. Two (2) data sorting variant models that will be implemented using the Bubble Sort algorithm are: Ascending data sorting variants moving from left to right, and Descending data sorting variants moving from left to right. And the device used in implementing the Bubble Sort algorithm is the Java programming language.

The automatic recognition of features in injection molded parts and assemblies are a crucial step in design to improve efficiency and effectiveness during the development and manufacturing stages. . When an internal undercut is present in the ejecting direction the finished plastic product cannot be directly ejected from the mold. Algorithms using the geometry of the undercut and the molded product are developed to avoid interference between the mould and the molded product when the product is ejected from its mould. The CAD models are developed using both the boundary representation as well as the CSG approach. This paper presents the development of computer algorithms in Java for sorting and recognizing undercut and mold features. The STEP AP 203 translator is used to communicate with various CAD systems. The proposed algorithm takes multiple feature models of plastic products as input and sorts the features using the Radix sort algorithm and then recognizes the features of the undercuts and the molds. Through the volumetric decomposition and the sorting algorithm the proposed approach can automatically recognize undercut features and efficiently calculate the undercut locations and dimensions using the feature parameters.

Three parallel sorting applications and two list output protocols for the first phase of an external sort execute on a fine-grained many-core processor array that contains no algorithm-specific hardware acting as a co-processor with a variety of array sizes. Results are generated using a cycle-accurate model based on measured data from a fabricated many-core chip, and simulated for different processor array sizes. The data shows most energy efficient first-phase many-core sort requires over 65 × lower energy than GNU C++ standard library sort performed on an Intel laptop-class processor and over 105 × lower energy than a radix sort running on an Nvidia GPU. In addition, the highest first-phase throughput many-core sort is over 9.8 × faster than the std::sort and over 14 × faster than the radix sort. Both phases of a 10 GB external sort require 6.2 × lower energy × time energy delay product than the std::sort and over 13 × lower energy × time than the radix sort.

In this paper we propose efficient two-party protocols for obliviously applying a (possibly random) linear group action to a data set. Our protocols capture various applications such as oblivious shuffles, circular shifts, matrix multiplications, to name just a few. A notable feature enjoyed by our protocols, is that they admit a round-optimal (more precisely, one-round) online computation phase, once an input-independent off-line computation phase has been completed. Our oblivious shuffle is the first to achieve a round-optimal online phase. The most efficient instantiations of our protocols are obtained in the so-called client-aided client-server setting, where the offline phase is run by a semi-honest input party (client) who will then distribute the generated correlated randomness to the computing parties (servers). When comparing the total running time to the previous best two-party oblivious shuffle protocol by Chase et al. (Asiacrypt 2020), our shuffle protocol in this client-aided setting is up to 105 times and 152 times faster, in the LAN and WAN setting, respectively. We additionally show how the Chase et al. protocol (which is a standard two-party protocol) can be modified to leverage the advantages of the client-aided setting, but show that, even doing so, our scheme is still two times faster in the online phase and 1.34 times faster in total on average. An additional feature of our protocols is that they allow to re-invoke a previously generated group action, or its inverse, in subsequent runs. This allows us to utilize randomize-then-reveal techniques, which are crucial for constructing efficient protocols in complex applications. As an application, we construct a new oblivious sorting protocol implementing radix sort. Our protocol is based on a similar approach to the three-party protocol by Chida et al. (IACR ePrint 2019/965), but using our oblivious shuffle as a building block as well as various optimizations, we obtain a two-party protocol (in the client-aided setting) with improved online running time and a reduced number of rounds. As other applications, we also obtain efficient protocols for oblivious selection, oblivious unit-vectorization, oblivious multiplexer, oblivious polynomial evaluation, arithmetic-to-boolean share conversions, and more.

A novel index distribution protocol based on single-particle state is proposed in this paper. Compared with the existing index distribution scheme, this protocol is not limited by the dimension of the quantum system. Based on the proposed index distribution protocol, we also propose a new quantum anonymous ranking protocol. This protocol can complete multi-user and multi-data anonymous ranking tasks in low-dimensional quantum systems. Security analysis shows that eavesdroppers cannot secretly obtain user’s private information without being discovered. In addition, we analyze and compare the protocol of this article with the existing anonymous ranking protocols. For different practical conditions, we give the general criteria of how to choose an appropriate anonymous ranking protocol.

Sorting is an essential operation which is widely used and is fundamental to some very basic day to day utilities like searches, databases, social networks and much more. Optimizing this basic operation in terms of complexity as well as efficiency is cardinal. Optimization is achieved with respect to space and time complexities of the algorithm. In this paper, a novel left-field N-dimensional cartesian spaced sorting method is proposed by combining the best characteristics of bucket sort, counting sort and radix sort, in addition to employing hashing and dynamic programming for making the method more efficient. Comparison between the proposed sorting method and various existing sorting methods like bubble sort, insertion sort, selection sort, merge sort, heap sort, counting sort, bucket sort, etc., has also been performed. The time complexity of the proposed model is estimated to be linear i.e. O(n) for the best, average and worst cases, which is better than every sorting algorithm introduced till date.

Definitive goal of various modern sorting algorithm is to re-arrange sequence of numbers or words in ascending or descending order. Compared to other exisiting sorting algorithms, the modern sorting algorithms used to provide execution time, running time and complexity based on the given number of inputs. Thus, the modern algoirithms helps us to know more about re-arranging or re-ordering numbers or words including how they fastly operate inputs in a specific manner of time. This paper focused on asymptotic analysis pertaining to the running time consumed by most recent sorting algorithms based on the number of elements in an array. Through computation of the running time, it is really possible to know how sorting algorithms tends to become not only efficient but also a manner its usefulness. Various contemporary sorting algorithms like gnome sort, shaker sort, radix sort, shell sort and comb sort have considered and being compared in this study.

Sorting plays a fundamental role in computer science. It has far reaching applications in database operations and data science tasks. An important class of sorting keys are strings and among all string sorting methods, radix sort is a simple but effective algorithm. Many works have been studied to accelerate radix string sort. One typical approach is to process multiple characters in each sorting pass. However, this approach incurs the crucial issue of the radix being too large. To address the problem, we introduce a novel multi-character encoding based method that can significantly reduce the radix. This new encoding scheme takes advantage of the sparse alphabet space usage as well as the sparsity of distinguishing prefixes of the inputs which are commonly seen in real-world datasets. Combining the effective encoding scheme with an adaptive sampling process to generate the encoding efficiently, our proposed sorting algorithm essentially blends radix sort with sample sort and achieves substantial improvement over other sorting approaches. The results on both real datasets and synthetic datasets show that our method yields an average 4.85× performance improvement over C++ STL sort[21], 1.47× improvement over the state-of-the-art Radix Sort on strings implementation[19] and 2.55× over the multikey quicksort[6]. Preliminary tests in a multi-core environment also show it is competitive or better than the most recent parallel string sorting algorithm pS5[8] which demonstrates the scalability of our method.

Digital image forensic is a sub-area of multimedia security whose objective is to expose the malicious image manipulations in digital images. Among different types of image forgery, copy–move forgery is the most popular to forge the digital images where a part of the original digital image is copied and pasted at another position in the same image. Different methods have been developed to detect the image forgery in digital images. On the basis of our literature review, we identify that less attention is given to clustering algorithms to speed up the block matching strategy during image forgery detection process. Therefore, to address this issue, we present a pixel-based copy–move image forgery detection method to check the genuineness of digital images. Proposed method includes the following steps: (1) convert the color image into gray-scale image, (2) divide the gray-scale image into overlapping blocks of size 8 × 8, (3) feature extraction using DCT on the basis of different feature sets, (4) block clustering using K-means algorithm, and (5) radix sort for feature matching. Experimental results demonstrate that proposed method can efficiently detect the forged part from digital images.

The von Neumann computer architectures have a bottleneck of data transfer between memory and processing unit. This degrades performance and increases power consumption for data-intensive applications. Memristor is an alternative building block for designing non-volatile memory. The universal NOR logic gate can be realized on a memristor based crossbar memory array. Hence complex arithmetic and logic operations can be performed within the memory. This work introduces in-memory sorting of non-negative integers on memristor crossbar. An instruction set for memristor based in-memory computation is introduced. In-memory sorting algorithms are implemented with these instructions. For a maximum input size of 1.0E+ 12 64-bit unsigned integers the in-memory selection, merge and radix sort achieve power savings of 78 %, 28 % and 35 %, respectively because the elements to be sorted are not fetched in the cache memory. The high delay of an in-memory compare operation degrades the performance of in-memory comparison sort. The traditional processor based selection and merge sort run 31x and 4x faster, respectively. In-memory radix sort is 2% faster.

Increasing computing power is now achieved by replacing the programming paradigm with parallel programming. Parallel computing is a method of solving problems by dividing the computational load into small parts of the computation sub-process. This study describes the comparative analysis of parallel computations in the Selection Sort and Radix Sort algorithms. The data used are in the form of whole numbers and decimal numbers totaling 100 to 2 million data. The test was carried out with three scenarios, namely using two processors, four processors, and 3 computers connected to each other via a LAN network. The results showed that the parallel Selection Sort algorithm for small data was better than the parallel Radix Sort. On the other hand, parallel Radix Sort is better for millions of data than Selection Sort.

We propose an O(N logN) sorting method by Modified Merge Sort Method, which shows huge potential to sort big data sets, and even better potential to sort big data sets with a smaller range. Six sorting algorithms: Selection Sort, Insertion sort, Merge sort, Quick sort, Bubble Sort and Modified Merge Sort were implemented in C++ programming languages and tested for the random sequence input of length 100, 1000, 4000, 9000 on random numbers and the IPL Dataset.

We present a new algorithm for transposing sparse tensors called Quesadilla. The algorithm converts the sparse tensor data structure to a list of coordinates and sorts it with a fast multi-pass radix algorithm that exploits knowledge of the requested transposition and the tensors input partial coordinate ordering to provably minimize the number of parallel partial sorting passes. We evaluate both a serial and a parallel implementation of Quesadilla on a set of 19 tensors from the FROSTT collection, a set of tensors taken from scientific and data analytic applications. We compare Quesadilla and a generalization, Top-2-sadilla to several state of the art approaches, including the tensor transposition routine used in the SPLATT tensor factorization library. In serial tests, Quesadilla was the best strategy for 60% of all tensor and transposition combinations and improved over SPLATT by at least 19% in half of the combinations. In parallel tests, at least one of Quesadilla or Top-2-sadilla was the best strategy for 52% of all tensor and transposition combinations., This work will be the subject of a brief announcement at the 32nd ACM Symposium on Parallelism in Algorithms and Architectures (SPAA '20)

Sorting is a key part in database operators (like duplicate elimination, sort-merge joins and group-by aggregations). Sorting billions of records in a fast and energy efficient manner has become a key research challenge. In this work, we explore sorting in-memory using a parallel version of Radix Sort to build a high-performance hardware accelerator, called HARS (Hardware Accelerated Radix Sort). Our design enables dividing the unsorted dataset among parallel engines without the need for a merge step. HARS is implemented on Micron’s SB-852 FPGA board. The proposed accelerator provides high throughput in-memory sorting at a rate of 44 Million 128-bit records per second. HARS is 1.4x faster than CPU and 1.36x faster than GPU when GPU bandwidth is normalized. Projected performance of a proposed board with a more capable FPGA chip would yield 1.25x higher throughput.

Many applications in data analytics, information retrieval, and cluster computing process huge amounts of information. The complexity of involved algorithms and massive scale of data require a programming model that can not only offer a simple abstraction for inputs larger than RAM, but also squeeze maximum performance out of the available hardware. While these are usually conflicting goals, we show that this does not have to be the case for sequentially-processed data, i.e., in streaming applications. We develop a set of algorithms called Vortex that force the application to generate access violations (i.e., page faults) during processing of the stream, which are transparently handled in such a way that creates an illusion of an infinite buffer that fits into a regular C/C++ pointer. This design makes Vortex by far the simplest-to-use and fastest platform for various types of streaming I/O, inter-thread data transfer, and key shuffling. We introduce several such applications -- file I/O wrapper, bounded producer-consumer pipeline, vanishing array, key-partitioning engine, and novel in-place radix sort that is 3-4 times faster than the best prior approaches.

We present four high performance hybrid sorting methods developed for various parallel platforms: shared memory multiprocessors, distributed multiprocessors, and clusters taking advantage of existence of both shared and distributed memory. Merge sort, known for its stability, is used to design several of our algorithms. We improve its parallel performance by combining it with Quicksort. We present two models designed for shared memory MIMD (OpenMP): (a) a non-recursive Merge sort and (b) a hybrid Quicksort and Merge sort. The third model presented is designed for distributed memory MIMD (MPI) using a hybrid Quicksort and Merge sort. Our fourth model is designed to take advantage of the shared memory within individual nodes of todays cluster systems, and to eliminate all internal data transfers between different nodes, Our model implements a one-step MSD-Radix to distribute data in ten packets (MPI) while parallel cores of each node use Quicksort to sort their data partitions sequentially then merge and sort them in parallel employing the OpenMp. The performances of all developed models outperform the baseline performance. Hybrid Quicksort and Merge sort outperformed Hybrid Memory Parallel Merge Sort using Hybrid MSD-Radix and Quicksort in Cluster Platforms when sorting small size data, but with larger data the speedup of Hybrid Memory Parallel Merge Sort Using Hybrid MSD-Radix and Quicksort in Cluster Platforms becomes bigger and it keeps improving. The speedup of Distributed Memory Parallel Hybrid Quicksort and Merge Sort is the best.

Computation of rough set approximation (RSA) is a critical step for attribute reduction and knowledge acquisition in rough set theory. Continuously improving computation efficiency of RSA is very meaningful, because it can enhance user experience of existing applications. Furthermore, it is helpful to apply rough sets to some fields with high performance requirement. Graphics processing unit (GPU) has gained a lot of attention from scientific communities for its applicability in high-performance computing. Different from existing works, this paper tries to apply GPU to accelerate a state-of-the-art serial algorithm of RSA computation, which is based on radix sorting. Three key steps of the serial algorithm are parallel designed, including object sorting, computation of equivalence classes, and computation of RSA. The experimental results show that the parallel method can accelerate the computation process efficiently.

Multisplit is a broadly useful parallel primitive that permutes its input data into contiguous buckets or bins, where the function that categorizes an element into a bucket is provided by the programmer. Due to the lack of an efficient multisplit on GPUs, programmers often choose to implement multisplit with a sort. One way is to first generate an auxiliary array of bucket IDs and then sort input data based on it. In case smaller indexed buckets possess smaller valued keys, another way for multisplit is to directly sort input data. Both methods are inefficient and require more work than necessary: the former requires more expensive data movements while the latter spends unnecessary effort in sorting elements within each bucket. In this work, we provide a parallel model and multiple implementations for the multisplit problem. Our principal focus is multisplit for a small (up to 256) number of buckets. We use warp-synchronous programming models and emphasize warp-wide communications to avoid branch divergence and reduce memory usage. We also hierarchically reorder input elements to achieve better coalescing of global memory accesses. On a GeForce GTX 1080 GPU, we can reach a peak throughput of 18.93 Gkeys/s (or 11.68 Gpairs/s) for a key-only (or key-value) multisplit. Finally, we demonstrate how multisplit can be used as a building block for radix sort. In our multisplit-based sort implementation, we achieve comparable performance to the fastest GPU sort routines, sorting 32-bit keys (and key-value pairs) with a throughput of 3.0 G keys/s (and 2.1 Gpair/s)., 44 pages, to appear on ACM Transactions on Parallel Computing (TOPC): "Special Issue: invited papers from PPoPP 2016". This is an extended version of PPoPP'16 paper "GPU Multisplit"

Complete sequences are defined as infinite sequences of natural numbers, with the help of which it is possible to represent any other natural number. The most significant result, allowing to judge the completeness of any sequence, was obtained by D. Brown. The article poses the problem of representing the complete sequence of all natural numbers up to a certain limit as a sum of elements (such initial segments of complete sequences are called generating sequences). Then there is the problem of finding generating sequences of minimal length for a given limit N. The article proposes algorithms for generation of generating sequences of minimal length. A class of algorithms for generation of generating sequences containing a given generating sequence of shorter length is proposed, it allows us to introduce regular algorithms of generating complete sequences. The proposed regular algorithms for generating complete sequences are used in the development of the algorithm for sorting natural numbers without comparing them, which is the development of the radix sorting algorithm with interpretation of the bits as elements of a suitable complete sequence. The article demonstrates approaches of adapting the work of this algorithm for sorting a specific sorted sequence.

Capacitor voltage balancing strategy for Submodules (SMs) is one of the key technologies for modular multi-level converters(MMC). The conventional strategy has the problems of large computation and high switching frequency of devices. In order to solve these problems, a mark and operation voltage balancing strategy (MOVBS) is proposed. This strategy marks SMs with two different labels according to the amplitude of capacitor voltage of SMs and current direction of arms, then do sorting and selecting operations to SMs based on the marking results. It reduces sorting times, switching frequency and power loss of devices. For capacitor voltage sorting process, a binary radix sorting algorithm(BRSA) is proposed to improve sorting speed and efficiency of MOVBS. Finally, the feasibility and effectiveness of the MOVBS is verified with a 11-level MMC-HVDC simulation model created in Matlab/Simulink.

Sorting remains a quintessential problem in computer science; henceforth, considerable research has focused on optimizing runtime efficiency when sorting a collection of elements. Most algorithms for sorting objects are comparison-based. Bucket Sort and Radix Sort are non-comparison based sorting algorithms that can sort objects in linear time. In both cases, the corresponding array indices represent a hash for the object. Nevertheless, Radix Sort still requires an auxiliary array. In this paper, replacing Radix Sort's auxiliary array with a hash table is proposed. Use of a hash table in Radix Sort should avoid the calculations for the array and be better suited for handling objects. As with an array-based Radix sort, this hash-based approach should maintain linearity, thereby sorting objects more efficiently. Following successfully programming this novel sorting algorithm, as the number of elements increases, the runtime progresses linearly, not exponentially. Moreover, as the number of digits increases, the sorting runtime still lengthens linearly. Thus, a hash-based Radix sort is feasible and overcomes many issues associated with current sorting algorithms.

Sorting kernels are a fundamental part of numerous applications. The performance of sorting implementations is usually limited by a variety of factors such as computing power, memory bandwidth, and branch mispredictions. In this paper we propose an efficient hybrid sorting method which takes advantage of wide vector registers and the high bandwidth memory of modern AVX-512-based multi-core and many-core processors. Our approach employs a combination of vectorized bitonic sorting and load-balanced multi-threaded merging. Thread-level and data-level parallelism are used to exploit both compute power and memory bandwidth. Our single-threaded implementation is ~30x faster than qsort in the C standard library and ~10x faster than C++'s std::sort. Compared with the Intel Performance Primitives (IPP) library which is one of the most efficient CPU-based radix sort implementation, we obtain a speedup of 1.3 to 2.6. Furthermore, we achieve a peak performance of sorting 1.14 billion floats per second on a Xeon Phi 7210 processor. Moreover, we show the extensibility of our vectorized kernels to processing units with a varying of vector lanes.

In order to solve many real problems, we have to sort array segments of data. This sorting task is called segmented sorting. Problems like image processing and suffix array construction usually have huge amount of data and their solutions make use the segmented sorting procedure. There are several techniques for solving the segmented sorting. A previous work showed that a strategy called fix sort had a good performance to sort segments of arrays. This strategy adjusts the input array to allow off-the-shelf general sorting algorithms to execute segmented sorting. Besides the extensive tests that were done in the previous work, the implemented fix sort solution did not explore in full the proposed parallel algorithm. In this work we revisit the sequential and parallel algorithms to the fix sort strategy creating new parallel and sequential implementations. We compared our results with the previous methods to sort multiple segments. The obtained results showed that our implementations of fix sort strategy achieved better execution times than the previous ones.

This talk will discuss recent work improving the Sort module of the Chapel programming language. It will discuss an interface design to support radix sort, describe the implementation of radix sort, compare the performance of this implementation to sort libraries in other language, and finally discuss distributed sorting.

Parallel radix sorting has been extensively studied in the literature for decades. However, the most efficient implementations require auxiliary memory proportional to the input size, which can be prohibitive for large inputs. The standard serial in-place radix sorting algorithm is based on swapping each key to its correct place in the array on each level of recursion. However, it is not straightforward to parallelize this algorithm due to dependencies among the swaps. This paper presents Regions Sort, a new parallel in-place radix sorting algorithm that is efficient both in theory and in practice. Our algorithm uses a graph structure to model dependencies across elements that need to be swapped, and generates independent tasks from this graph that can be executed in parallel. For sorting n integers from a range r, and a parameter K, Regions Sort requires only O(Klog rlog n) auxiliary memory. Our algorithm requires O(nlog r) work and O((n/K+log K)log r) span, making it work-efficient and highly parallel. In addition, we present several optimizations that significantly improve the empirical performance of our algorithm. We compare the performance of Regions Sort to existing parallel in-place and out-of-place sorting algorithms on a variety of input distributions and show that Regions Sort is faster than optimized out-of-place radix sorting and comparison sorting algorithms, and is almost always faster than the fastest publicly-available in-place sorting algorithm.

Background Motifs are crucial patterns that have numerous applications including the identification of transcription factors and their binding sites, composite regulatory patterns, similarity between families of proteins, etc. Several motif models have been proposed in the literature. The (l,d)-motif model is one of these that has been studied widely. However, this model will sometimes report too many spurious motifs than expected. We interpret a motif as a biologically significant entity that is evolutionarily preserved within some distance. It may be highly improbable that the motif undergoes the same number of changes in each of the species. To address this issue, in this paper, we introduce a new model which is more general than (l,d)-motif model. This model is called (l,d 1,d 2)-motif model (LDDMS) and is NP-hard as well. We present three elegant as well as efficient algorithms to solve the LDDMS problem, i.e., LDDMS1, LDDMS2 and LDDMS3. They are all exact algorithms. Results We did both theoretical analyses and empirical tests on these algorithms. Theoretical analyses demonstrate that our algorithms have less computational cost than the pattern driven approach. Empirical results on both simulated datasets and real datasets show that each of the three algorithms has some advantages on some (l,d 1,d 2) instances. Conclusions We proposed LDDMS model which is more practically relevant. We also proposed three exact efficient algorithms to solve the problem. Besides, our algorithms can be nicely parallelized. We believe that the idea in this new model can also be extended to other motif search problems such as Edit-distance-based Motif Search (EMS) and Simple Motif Search (SMS).

Comparative Analysis and implementation of Sorting Algorithm aims at introducing five different algorithms, which sort the elements of an array in place. Sorting is an efficient algorithm to perform it has been developed in many applications. Comparative Analysis helps us in sorting sequences lookup for search, merging of sequences and processing of data. A comparison has been made between this particular idea and with the help of other popular implementations. We introduce five different algorithms which give us best time complexity for sorting of one Data set which we introduce during our program. It arranges the rundown of components with the goal that beginning anyplace considering each nth component gives an arranged rundown. With the proposed work we have done we finally reach out the conclusion and see that the situations where this outperforms and also look at the shortcomings which going to be occur and list the scope for future improvements that that could be made.

Sorting extremely large datasets is a frequently occurring task in practice. These datasets are usually much larger than the computer's main memory; thus, external memory sorting algorithms, first introduced by Aggarwal and Vitter, are often used. The complexity of comparison-based external memory sorting has been understood for decades by now; however, the situation remains elusive if we assume the keys to be sorted are integers. In internal memory, one can sort a set of n integer keys of Θ(lg n ) bits each in O ( n ) time using the classic Radix Sort algorithm; however, in external memory, there are no faster integer sorting algorithms known than the simple comparison-based ones. Whether such algorithms exist has remained a central open problem in external memory algorithms for more than three decades. In this paper, we present a tight conditional lower bound on the complexity of external memory sorting of integers. Our lower bound is based on a famous conjecture in network coding by Li and Li, who conjectured that network coding cannot help anything beyond the standard multicommodity flow rate in undirected graphs. The only previous work connecting the Li and Li conjecture to lower bounds for algorithms is due to Adler et al. Adler et al. indeed obtain relatively simple lower bounds for oblivious algorithms (the memory access pattern is fixed and independent of the input data). Unfortunately, obliviousness is a strong limitation, especially for integer sorting: we show that the Li and Li conjecture implies an Ω( n lg n ) lower bound for internal memory oblivious sorting when the keys are Θ(lg n ) bits. This is in sharp contrast to the classic (nonoblivious) Radix Sort algorithm. Indeed, going beyond obliviousness is highly nontrivial; we need to introduce several new methods and involved techniques, which are of their own interest, to obtain our tight lower bound for external memory integer sorting.

We study algorithms for solving three problems on strings. The first one is the Most Frequently String Search Problem. The problem is the following. Assume that we have a sequence of $n$ strings of length $k$. The problem is finding the string that occurs in the sequence most often. We propose a quantum algorithm that has a query complexity $\tilde{O}(n \sqrt{k})$. This algorithm shows speed-up comparing with the deterministic algorithm that requires $\Omega(nk)$ queries. The second one is searching intersection of two sequences of strings. All strings have the same length $k$. The size of the first set is $n$ and the size of the second set is $m$. We propose a quantum algorithm that has a query complexity $\tilde{O}((n+m) \sqrt{k})$. This algorithm shows speed-up comparing with the deterministic algorithm that requires $\Omega((n+m)k)$ queries. The third problem is sorting of $n$ strings of length $k$. On the one hand, it is known that quantum algorithms cannot sort objects asymptotically faster than classical ones. On the other hand, we focus on sorting strings that are not arbitrary objects. We propose a quantum algorithm that has a query complexity $O(n (\log n)^2 \sqrt{k})$. This algorithm shows speed-up comparing with the deterministic algorithm (radix sort) that requires $\Omega((n+d)k)$ queries, where $d$ is a size of the alphabet.

Generally, there is no sorting algorithm much faster than O(nlogn). The quicksort has a best performance O(nlogn) in best and average-case, and in worst-case. This paper suggests virtual radix counting bucket sort such that counting the frequency of numbers in each radix digit, and moves the arbitrary number to proper virtual bucket in the array, and divides the array into radix digit numbers virtually. Also, this algorithm moves the data to proper location within an array for using the minimum auxiliary memory. This algorithm performs k-times such that the number of k digits in given data and the time complexity is O(n). Therefore, this algorithm has a O(kn) time complexity.

V diplomski nalogi raziščemo področje urejanja števil z algoritmom radix in paralelizacijo algoritma na grafični procesni enoti (GPE). Za računanje na GPE smo uporabili tehnologijo CUDA, ki omogoča hitrejšo in učinkovitejšo uporabo grafičnih procesorjev. V nadaljevanju smo primerjali hitrosti urejanja različnih podatkovnih tipov, različnih velikosti podatkov in časovne razlike pri paralelnem in zaporednem urejanju radix. Ugotovili smo, da je paralelno urejanje približno 50-krat hitrejše. In this thesis we investigate the field of sorting numbers with radix sort algorithm and its parallelization on the graphic process unit (GPU). For processing on GPU we have used the CUDA technology, which enables faster and more efficient use of graphics processors. Next, we have compared the speed of sorting different data types, different data sizes and time differences between parallel and serial radix sort. We have found out that parallelization is approximately 50-times faster.

In general, sorting networks can be used as interconnection networks in that inputs are sorted according to their target addresses. However, if not all inputs need a connection to one of the outputs, partial permutations have to be implemented which cannot be directly done with sorting networks. For radix-based sorting networks, only one solution is known by Narasimha's permutation network that has unfortunately an inefficient configuration logic. In this paper, we prove that the same idea also works for more efficient ways to configure the same permutation network. We also present general alternatives for routing partial permutations in radix-based networks.

With the advent of big data and cloud computing, there is tremendous interest in optimised algorithms and architectures for sorting either using software or hardware. Field Programmable Gate Arrays (FPGAs) are being increasingly used in high end data servers providing a bridge between the flexibility of software and performance benefits of hardware. In this paper we look at implementations of some of the most popular sorting algorithms using OpenCL which take advantage of FPGA architecture. We evaluate these implementations in terms of power consumption which is measured using dedicated server power loggers and execution on Intel Arria 10 hardware. Our experiments show that taking advantage of software FIFOs have a significant impact on power consumption as well as requiring less hardware and memory resources.

In recent years, many cores architecture co-processors have become the main trend in high-performance computing area due to their powerful parallel computing capability. GPU is one of these promising high-performance computing co-processors and has been used in various applications for improvement. Sorting is a fundamental operation on computing area which can be used in a variety of applications. High efficient sorting algorithms can be achieved with the use of GPUs as well as challenges. On the one hand, GPU is a memory access sensitive hardware. On the other hand, many access on device memory are required in stages of sorting on GPU. In order to reduce the times of accessing device memory of sorting, we propose a Memory Access Reduced hybrid sort, an approach combining memory efficient radix sort and local sort. The local sort is implemented in two different ways. One is multiway bitonic sorting network (MAR-MBSN) in which the warp-shuffle instructions are taken advantage of. Another is radix and place sort (MAR-RPS). As the increasing require of high performance computing, multi-core GPUs have emerged. To fully use of the computing resources of GPU, two methods are applied for implementing our approach on dual-cores GPU. Experiments show that, compared to the CUB library sorting, MAR-MBSN has an up to 44% improvement and MAR-RPS gains an up to 3-fold speedup in local sort. As a result, MAR-MBSN and MAR-RPS achieves a speed up of no less than a factor of 1.5 and 1.66 respectively. Besides, multi-core GPU is introduced to implement our approaches and the factors relative to performance are analyzed.

The authors describe an optimized implementation of a set of scan (also called all-prefix-sums) primitives on a single processor of a CRAY Y-MP, and demonstrate that their use leads to greatly improved performance for several applications that cannot be vectorized with existing computer technology. The algorithm used to implement the scans is based on an algorithm for parallel computers. A set of segmented versions of these scans is only marginally more expensive than the unsegmented versions. The authors describe a radix sorting routine based on the scans that is 13 times faster than a Fortran version and within 20% of a highly optimized library sort routine, three operations on trees that are between 10 to 20 times faster than the corresponding C versions, and a connectionist learning algorithm that is 10 times faster than the corresponding C version for sparse and irregular networks.

As CPU processing speed has slowed down year-on-year, heterogeneous “CPU-GPU” architectures combining multi-core CPU and GPU accelerators have become increasingly attractive. Under this backdrop, the Heterogeneous System Architecture (HSA) standard was released in 2012. New Accelerated Processing Unit (APU) architectures – AMD Kaveri and Carrizo – were released in 2014 and 2015 respectively, and are compliant with HSA. These architectures incorporate two technologies central to HSA, hUMA (heterogeneous Unified Memory Access) and hQ (heterogeneous Queuing). This paper realizes radix sort and matrix-vector multiplication – two data-parallel applications on Kaveri platform. By analyzing the performance, a dynamic task scheduling stratgy is proposed. The experimental results show that the running efficiency of algorithm can be greatly improved by using APU with reasonable task scheduling. In the same way, the other data-parallel algorithm would also be optimized on these heterogeneous multi-core architecture.

Many non-blocking and self-routing interconnection networks are based on the radix sorting paradigm which requires the design of concentrator modules to distribute the given inputs to subnetworks for the recursive calls. To that end, binary sorters are often used that sort the inputs in each recursive call by one bit of their destination addresses starting with the most significant bit down to the least significant one. It is well-known that the use of more general concentrators instead of binary sorters may lead to more efficient circuits. However, the design of concentrators turned out to be a challenging task for many decades. In this paper, we construct from any binary sorter a corresponding concentrator by means of Batcher's half cleaner circuit. This way, we can improve many interconnection networks that are based on binary radix sorting in that we replace their binary sorters by the corresponding concentrators obtained by our optimization. We have implemented various binary sorters and their corresponding concentrators and demonstrate by experimental results the improvements we achieved this way.

Among comparison sorts, no algorithm excels a current set lower bound of O(nlogn) in operation. Quicksort, the fastest of its kind, has a complexity of O(nlogn) at its best and on average and at worst. This paper thus presents two methods: first is an O(n+k) simple counting sort which operates much more speedily than an O(n+k), (k=maximum value) counting sort, and second is an O(ln) radix counting sort which counts the frequency of numbers in the digit l of a data and saves it in a corresponding virtual bucket in an array, only to virtually divide the array into radix digit numbers. For the 6 experimental data, the proposed algorithm makes O(nlogn) or of Quicksort simple into O(n+k) or O(ln). After all, the proposed sorting algorithm has proved to be much faster than the counting sort and Quicksort.

In-place radix sort is a popular distribution-based sorting algorithm for short numeric or string keys due to its linear run-time and constant memory complexity. However, efficient parallelization of in-place radix sort is very challenging for two reasons. First, the initial phase of permuting elements into buckets suffers read-write dependency inherent in its in-place nature. Secondly, load balancing of the recursive application of the algorithm to the resulting buckets is difficult when the buckets are of very different sizes, which happens for skewed distributions of the input data. In this paper, we present a novel parallel in-place radix sort algorithm, PARADIS, which addresses both problems: a) "speculative permutation" solves the first problem by assigning multiple non-continuous array stripes to each processor. The resulting shared-nothing scheme achieves full parallelization. Since our speculative permutation is not complete, it is followed by a "repair" phase, which can again be done in parallel without any data sharing among the processors. b) "distribution-adaptive load balancing" solves the second problem. We dynamically allocate processors in the context of radix sort, so as to minimize the overall completion time. Our experimental results show that PARADIS offers excellent performance/scalability on a wide range of input data sets.

This paper describes our new algorithm for sorting an array of structures by efficiently exploiting the SIMD instructions and cache memory of today's processors. Recently, multiway mergesort implemented with SIMD instructions has been used as a high-performance in-memory sorting algorithm for sorting integer values. For sorting an array of structures with SIMD instructions, a frequently used approach is to first pack the key and index for each record into an integer value, sort the key-index pairs using SIMD instructions, then rearrange the records based on the sorted key-index pairs. This approach can efficiently exploit SIMD instructions because it sorts the key-index pairs while packed into integer values; hence, it can use existing high-performance sorting implementations of the SIMD-based multiway mergesort for integers. However, this approach has frequent cache misses in the final rearranging phase due to its random and scattered memory accesses so that this phase limits both single-thread performance and scalability with multiple cores. Our approach is also based on multiway mergesort, but it can avoid costly random accesses for rearranging the records while still efficiently exploiting the SIMD instructions. Our results showed that our approach exhibited up to 2.1x better single-thread performance than the key-index approach implemented with SIMD instructions when sorting 512M 16-byte records on one core. Our approach also yielded better performance when we used multiple cores. Compared to an optimized radix sort, our vectorized multiway mergesort achieved better performance when the each record is large. Our vectorized multiway mergesort also yielded higher scalability with multiple cores than the radix sort.

Batchers bitonic sorting algorithm is a parallel sorting algorithm, which is used for sorting the numbers in modern parallel machines. There are various parallel sorting algorithms such as radix sort, bitonic sort, etc. It is one of the efficient parallel sorting algorithm because of load balancing property. It is widely used in various scientific and engineering applications. However, Various researches have worked on a bitonic sorting algorithm in order to improve up the performance of original batchers bitonic sorting algorithm. In this paper, tried to review the contribution made by these researchers.

The attribute reduction algorithm of radix sort to integer digit sequence table is not ideal. In this paper, based on how integers is stored in computer memory, low and high storage mode is designed for the solving algorithm of U/C chain structure of a new reasonable optimization. The time complexity of the algorithm from O (K|C| |U|) is reduced to O (K|C| |U| log (|M|)). The efficiency of the algorithm is improved by 3.8%.

Very-large-scale integration (VLSI) architectures for finding the first $W$ $(W>2)$ maximum (or minimum) values are required in the implementation of several applications such as nonbinary low-density-parity-check decoders, K-best multiple-input–multiple-output (MIMO) detectors, and turbo product codes. In this brief, a parallel radix-sort-based VLSI architecture for finding the first $W$ maximum (or minimum) values is proposed. The described architecture, called Bit-Wise-And (BWA) architecture, relies on analyzing input data from the most significant bit to the least significant one, with very simple logic circuits. One key feature in the BWA architecture is its high level of scalability, which enables the adoption of this solution in a large spectrum of applications, corresponding to large ranges for both $W$ and the size of the input data set. Experimental results, achieved by implementing the proposed architecture on a high-speed 90-nm CMOS standard-cell technology, show that BWA architecture requires significantly less area than other solutions available in the literature, i.e., less than or about 50% in all the considered cases and about 50% in the worst case. Moreover, the BWA architecture exhibits the lowest area–delay product among almost all considered cases.

In this paper, we present a new self-routing and non-blocking uni-cast interconnection network based on binary radix sorting that is more efficient than comparable other interconnection networks. To substantiate this claim, we first derive the asymptotic complexities of the size and depth of our network's circuit netlist. Moreover, we have implemented our network as well as other related radix-based sorting networks using 65nm CMOS chip technology. We compare the maximal frequency, the required chip area, and the power consumption of these circuits. Our evaluation shows that our network is best among the considered radix-based networks regardless whether the maximal frequency, the chip area or the power consumption is considered.

Sorting algorithm remained hot topic in computer science from the birth of computer science to achieve maximum performance. Fortunately this achievement became possible due to good and fast sorting algorithms, such as heap sort, merge sort, radix sort and other sorting algorithms. Till this achievement is also under research to find more efficient algorithms. In sorting algorithm arrays and link list data structures are commonly used. We know arrays are efficient if we need consecutive kind of data structure and link lists are useful when we need to add and remove items in the data structure. In other word we can say both data structures have own its merits and demerits. So in our sorting algorithm we are going to use both kinds of data structure. We will use in our MainIndex sorting algorithm arrays as the MainIndex and link list as sorting cells. MainIdex sorting algorithm need some kind of information just the length of the number which is going to sort and the value of the number which is going to sort in sorting cell.

The paper introduces RADULS, a new parallel sorter based on radix sort algorithm, intended to organize ultra-large data sets efficiently. For example 4 G 16-byte records can be sorted with 16 threads in less than 15 s on Intel Xeon-based workstation. The implementation of RADULS is not only highly optimized to gain such an excellent performance, but also parallelized in a cache friendly manner to make the most of modern multicore architectures. Besides, our parallel scheduler launches a few different procedures at runtime, according to the current parameters of the execution, for proper workload management. All experiments show RADULS to be superior to competing algorithms.

The paper is dedicated to fast FPGA-based hardware accelerators that implement sorting networks. The primary emphasis is on the uniformity of core components, feasible combinations of parallel, pipelined and sequential operations, and the regularity of the circuits and interconnections. The paper shows theoretically, and based on numerous experiments, that many existing solutions that are commonly considered to be very efficient have worthy competitors that are better for many practical problems. We compared the even-odd merge and bitonic merge sorting networks (which are among the fastest known) with the even-odd transition network, which is often characterized as significantly slower and more resource consuming. We found that the latter is the most regular network that can be implemented very efficiently in FPGA, so we are proposing new, easily scalable hardware solutions and processing techniques based on this. Finally, the paper provides four main contributions and suggests: (1) a regular hardware implementation of resource and time effective architectures based on the even-odd transition network; (2) a pipelined implementation of even-odd transition networks; (3) a pre-processing technique that enables sorting to be further accelerated; (4) combinations of this technique with a merge sort, an address-based sort, a quicksort, and a radix sort.

In this study, we attempt to address the issue regarding the spatial join count, where in the number of particles around a halo is counted only once for a given simulation result. An efficient spatial index is necessary for accelerated counting; therefore, we propose a CPU optimized sort-tile-recursive R-tree that employs a parallel radix sort and node packing with thread pool and single instruction multiple data instructions. In an experiment conducted with astronomical data, the proposed method demonstrates an improvement in performance by 26.8 times compared with that using a conventional CPU optimized R-tree. We also propose a partial materialization approach to handle large amount of data that exceeds the capacity of main memory. To accelerate the approach, we propose a construct-search-destruct pipeline that exploits a thread pool to conceal the latency of the construction and destruction of the index. The pipelining method achieves an improvement in performance by 27.5 times compared with that of a conventional CPU optimized R-tree. All our codes are available on GitHub.