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Deep reactive ion etching (DRIE) is an enabling technology for three dimensional (3D) integration of planar integrated circuits. This work focuses on various challenges associated with deep reactive ion etching technology for realizing through silicon interconnection for 3D Microsystems application. In the first part of the thesis, stress simulation studies were done on TSV structures of various via geometries and shapes to determine the regions of high stress due to CTE mismatch. It was determined that the top and bottom of the vias and the surrounding materials experience maximum mechanical stress. It was also found that the stress is concentrated in the sharp peaks and valleys of the scallops formed by Bosch etch process. A test vehicle was designed and fabricated by copper damascene process with various geometries and barrier structures to experimentally study the effect of sidewall scallops on electrical leakage between adjacent TSV structures. It was shown that the leakage current can be reduced by about nearly 3 orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall for the initial few microns of the depth of the via by using a non-Bosch etch process. This study has shown that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, for vertical TSV etch application by tailoring a short first etch step with smooth sidewall. DOCTOR OF PHILOSOPHY (EEE)

A series of images, ideas, emotions, and sensations that happen involuntarily in the mind at the time of sleep are known as dreams. A definite understanding of the content and purpose of dreams is not yet established. They have frequently been a subject of scientific assumption and a focus of philosophical and religious interest.

Security and distributed infrastructure are two of the most common requirements for big data software. But the security features of the big data platforms are still premature. It is critical to identify, modify, test and execute some of the existing security mechanisms before using them in the big data world. In this paper, we propose a novel intrusion detection technique that understands and works according to the needs of big data systems. Our proposed technique identifies program level anomalies using two methods - a profiling method that models application behavior by creating process signatures from control-flow graphs; and a matching method that checks for coherence among the replica nodes of a big data system by matching the process signatures. The profiling method creates a process signature by reducing the control-flow graph of a process to a set of minimum spanning trees and then creates a hash of that set. The matching method first checks for similarity in process behavior by matching the received process signature with the local signature and then shares the result with all replica datanodes for consensus. Experimental results show only 0.8% overhead due to the proposed technique when tested on the hadoop map-reduce examples in real-time.

Big data platforms such as Hadoop and Spark are being widely adopted both by academia and industry. In this paper, we propose a runtime intrusion detection technique that understands and works according to the properties of such distributed compute platforms. The proposed method is based on runtime analysis of system and library calls and memory access patterns of tasks running on the datanodes (slaves). First, the primary datanode of a big data system creates a behavior profile for every task it executes. A behavior profile includes (a) trace of the system & library calls made, and (b) sequence representing the sizes of private and shared memory accesses made during task execution. Then, the process behavior profile is shared with other replica datanodes that are scheduled to execute the same task on their copy of the same data. Next, these replica datanodes verify their local tasks with the help of the information embedded in the received behavior profiles. This is realized in two steps: (i) comparing the system & library calls metadata, and (ii) statistical matching of the memory access patterns. Finally, datanodes share their observations for consensus and report an intrusion to the namenode (master) if they find any discrepancy. The proposed solution was tested on a small hadoop cluster using the default MapReduce examples and the results show that our approach can detect insider attacks that cannot be detected with the traditional analysis metrics.

A novel two step etch process using the Bosch-etch mechanism to prevent notching on an SOI wafer is presented. The first etch step is used to attain the maximum etch depth with high etch rate and stop before the buried oxide (BOX). Followed by the second etch step with lower etch rate and tuned to soft land on the BOX to etch the remaining depth. In addition to that it is tailored to also provide a tapered etch profile which is beneficial in reducing the notch if over etching occurs.

Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125°C ) and drop test.

A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 mtorr and is characterized using a micro-electro-mechanical systems (MEMS) motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q-factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer-level package showed the package is robust to the reliability conditions. A progressive test on the Q-factor for different cycles of reliability test proved that there is no shift in the measurement value. A 3-D wafer-level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed no degradation in the device performance when subjected to reliability tests.

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a J-shaped spring design produces a combination of high 3D compliances and acceptable electrical parasitics. Further, numerical analyses on the J -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 mum). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to ~35 GHz without significant power loss.

Stacking of many functional chips in a 3-D stack package leads to high heat dissipation. Therefore, a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3-D stacked package with silicon interposers was developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer were formed by through silicon via. Silicon interposer has much high thermal conductivity than organic interposer, therefore the package thermal resistance is lower. Thermal performances of the 3-D package were analyzed and thermal enhancements like thermal via, thermal bridging were evaluated. The designed package showed 5 times lesser thermal resistance compared to a similar package with organic substrate. An additional silicon heat spreader was designed and attached to the package for high power application. Thermal analysis was performed to optimize package thermal performances and experimental validation was carried out. The designed 3-D stack package is suitable for 20 W application.

A novel dual-etch process technology has been developed for the tapering of deep silicon vias which can be used in the fabrication of through-silicon interconnected silicon carriers for 3D system in packaging application. The process consists of two etching steps viz. an anisotropic etch process followed by a global isotropic etch process which causes the vias profile to taper. The 1st etching step is designed to provide high etch rate and throughput while the 2nd etch step is designed to control the taper angle of the via. It has been shown that through this approach of partitioning the via formation process into an anisotropic etch and an isotropic etch process, it is possible to maintain high overall etch rates without compromising on the final via profile and throughput. The via profile achieved has been extensively characterized with respect wide range of critical process parameters and via geometries. It has been demonstrated that regardless of the choice of via formation method, it is feasible to achieve a controllable via taper to realize a void-free copper via-filling by electroplating process.

This paper addresses fatigue and bridging issues by numerical analysis for an ultra-fine-pitch flip-chip interconnect that consists of multiple copper columns (MCC) and a solder joint. First, the processing flow is briefly presented, which enables prototyping of high-aspect-ratio (~6) copper columns, and hence, enhanced thermomechanical reliability of the interconnects. A public software, Surface Evolver (SE), has been used through this work to predict the solder joint geometry evolution. By integrating SE solder joint shape modeling, stress/strain analysis within ANSYS, and design of experiment (DoE) techniques as well, detailed numerical analysis has been conducted on the solder joint fatigue response to various factors such as the Cu-Solder wetting angle, loading direction, and solder geometry parameters. Finally, by applying the DoE techniques and the most updated features of SE, bridging risks of this interconnect with a fine pitch of 40mum is investigated, in which critical solder volume is calculated as a function of the interconnect geometry parameters. Based on these results, a solid basis for the design and processing of this advanced flip-chip interconnect has been established

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.

A low temperature resist trimming process with low trimming rate and good uniformity was developed. Wafer chuck temperature in the ashing chamber was adjusted to be 6 °C to achieve low trimming rate and improve process uniformity. Low power oxygen and argon plasma was used for ashing the resist. Resist lines (0.5 μm wide) patterned with a g-line stepper was trimmed down to sub-100 nm widths. The trimming rate was found to be independent of the initial line width and trimming time. A 0.6 μm CMOS process flow with LOCOS and nitride spacer was suitably modified incorporating resist trimming to fabricate NMOSFETs with gate length as small as 95 nm. Since most polymer-based photoresists can be etched in oxygen plasma, the basic technique could be extended to supplement other lithographic processes for channel length scaling.

This paper describes a process technology to make MEMS devices with laterally integrated polysilicon beam as the structural material instead of single crystal silicon for sensors/ actuators. The process consists of fabricating deep silicon trenches, which are then seamlessly filled with the layers of thermal oxide and polysilicon. The polysilicon on the surface is etched back, leaving behind the polysilicon only inside the trenches. The beams are then released by isotropically etching away the silicon surrounding the polysilicon/ silicon oxide structure. This results in free standing polysilicon beams, which form the MEMS structures. The thermal oxide surrounding the polysilicon can be removed by wet HF etch or by isotropic plasma etch. This process can serve as a general platform for realising various types of high aspect ratio MEMS devices. The various stages of the process development, in realising a low stress polysilicon beams and electrical isolation structures are described in the paper.

International audience; ISVLSI 2014 explores emerging trends, novel ideas and concepts in the area of VLSI. The Symposium covers a wide range of topics from emerging technologies to design methods to system level design of VLSI circuits and systems. The topics also include future design methodologies and VLSI CAD to support these technologies. For the past two decades, the conference has been a unique forum for promoting visionary approaches to VLSI design process and an esteemed venue for presenting multidisciplinary research. The Symposium brings together leading scientists and researchers from academia and industry. The papers from this symposium have been published as special issues of top archival journals. These traditions will be continued in 2014. The symposium proceedings will be published by the IEEE Computer Society Press.

This paper presents the development of a low temperature silicon nitride deposition process using plasma enhanced chemical vapor deposition (PECVD) system. The nitride films showed low stresses ranging from compressive to tensile and very low etch rates in the buffered oxide etch (BOE) solution. These nitride films can be used as MEMS structure materials where suspended structures are involved. In this work, individual process parameters such as SiH 4 /H 2 /N 2 gas flows, chamber pressures, temperatures and HF powers that related to the nitride film stress and etch rate in BOE solution are also investigated.

In this paper, a method of fabricating radio opaque silicon micro needles for tissue labeling applications is reported. Cylindrical shaped micro needles ranging from 7 × 7 to 11 × 11 arrays with a pitch varying from 60 µm to 100µm are fabricated in silicon using a three step mask process. A backside cavity is generated under DRIE for filling the radiopaque material. Barium sulphate is filled in and a biocompatible sealing is provided to hold the radiopaque material inside. The fabricated needles provide a better contrast enhancement under x-ray imaging.

This paper presents our development work to achieve high aspect ratio void-free polymer via filling with various types of organic materials for potential application in 3D wafer level packaging. This study focuses on the development of via filling process using the conventional spin-coating and curing process. Thermoplastic polymers have been selected for this evaluation due to its ability to reflow and fill gaps easily. Test wafers with circular via patterns with diameters from 1–70 µm with aspect ratios from 1–10 have been evaluated. The various challenges to achieving void-free via filling have been presented and it has been demonstrated that a void-free filling is feasible for vias with aspect ratio of 1–8.

A detailed study to perform low temperature (< 200°C) PECVD TEOS-oxide deposition process with very low mechanical stress and good conformal deposition on high aspect ratio features (10∶1) was done. Individual conditions that affect the oxide stress and deposition rate such as TEOS & O2 flow rate, HF/LF power, pressure and temperature are investigated. The optimal conditions found are used to then deposited into trenches and further fine tuned to give excellent step coverage for high aspect ratio features.

This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.

In this paper, Through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.

80 wt.% Au, 20 wt.% Sn solder is used in optoelectronics because it allows soldering in fluxless processes. Au-Sn solder is also applied in the field of RF and MEMS packaging. Normally the deposited solders are re-flowed after electroplating but it is also possible to use the bumps in the as-deposited condition. Au-Sn solder which has been reflowed consists of an Au pedestal with a eutectic solder cap on top. Reflow soldering is a cost effective approach for the flip chip technology or die attachment process. Using pick & place equipment the substrate is populated with the components. Soldering is performed afterwards in an oven. During soldering it is possible to utilize the self-alignment mechanism. In this study, Au-Sn besides 80 wt.% Au, 20 wt.% Sn solder composition is evaluated and characterized in evaporation deposition process for SiOB (silicon optical bench) applications. Multiple layers of thin Sn and Au solders are deposited one-by-one. The layer thickness is calculated and optimized to meet the desired solder composition. The deposited solder is evaluated using FIB (Focused Ion Beam) to observe the layer thickness uniformity. Micro-structural observations for deposited solder samples are conducted before and after solder reflow for melting. The composition is identified by chemical composition analysis (EDS - energy dispersive spectroscopy) and thermal analysis (DSC - differential scanning calorimetry). The interfacial reaction and morphology with Ti/Pt/Au UBM (under bump metallurgy) layers are also observed with different reflow conditions. Results of die shear for photonic diode attachment are shown.

It is reported for the first time a process technology to fabricate sub-100 nm silicon nano-channels with ultra high aspect ratio (~160) for micro fluidics, nano-filtration and pathogen detection applications. A novel double passivation deep reactive ion etching process has been developed to realize ultra high aspect ratio silicon nano-channels which is further narrowed by deposition of polysilicon and thermally oxidized to form sub-100 nm buried nano-channels. This technology further provides for in-situ capping of the nano channels which offers significant stress-relief at the top of the nano-channels during subsequent glass bonding and packaging process. By providing in-situ capping capability for the channels we also eliminate potential leakage issues due to poor bonding contact. This channel capping also helps in preventing breakage of the high aspect ratio structures under high anodic bonding pressure. Though the present work was targeted for biological applications, it can easily be used for mainstream MEMS and NEMS applications such a RF resonators, Sensors and Actuators.

A novel compliant flip-chip interconnect in the form of a planar microspring is presented in this paper. Different spring geometries are evaluated and compared in terms of compliances and electrical parasitics. It is shown that the J-shape spring design gives a better balanced performance. Further numerical studies reveal the geometric dependence of the compliances of J-shape spring interconnects, and also the influence of the sacrificial material upon the electrical performance of the interconnects. The wafer-level process flow for fabrication of the planar microspring interconnects is described and discussed. Prototype interconnects are fabricated by combining planar technology and 3D surface micromachining technology.

A wafer level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 milli torr and is characterized using a MEMS motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer level package showed the package is robust to the reliability conditions. A progressive test on Q factor for different cycles of reliability test proven that there is no shift in the measurement value. A 3D wafer level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed that no degradation in the device performance when subjected to reliability tests.

A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the etch throughput and required via slope that is required to achieve conformal deposition of dielectric, copper diffusion barrier and copper seed metallization. It is further shown how a void-free copper via plating has been achieved for implementation into 3-D integrated systems.

In this paper, quantitative assessments of single-phase liquid cooled heat sinks based on three types of enhancement microstructures are presented for microelectronics applications. The first type is a metallic microchannel heat sink (MMCHS) made of aluminum with the channel dimensions of 15 mm (L) × 0.2 mm (W) × 2 mm (H). The second type are two silicon microchannel heat sinks (SMCHS) made through the deep reactive ion etching (DRIE) technique, with identical channel height of 0.45mm and average channel widths of 66.6 μm and 46.6μm, respectively. Metallic foam heat sinks (MFHSs) are the third type, which were formed by brazing porous foam materials of high pore density and enlarged surface area onto a copper base plate. All the three types of heat sinks were fabricated and experimentally characterized incorporating electronic packages. Characterization results indicate that the MMCHS and MFHSs can achieve equivalent thermal performance above 100 W/cm2 and the silicon MCHS above 200 W/cm2 at the expense of larger pressure drop. A comparison of the pressure drops, thermal enhancement and manufacturability of the three types of heat sinks is also presented.Copyright © 2005 by ASME

A wafer through hole filled via interconnection method on silicon has been developed for 3D wafer level packaging for MEMS (Micrc-Electro mechanical systems) application. In this 3D package the bottom wafer is a MEMS device and the cap wafer is silicon. Using Deep Reactive Ion Etching process the through hole via has been formed on the silicon cap wafer. A conductive material is uniformly deposited on the backside of the cap wafer before the via etch process to serve as an etch stop layer in DRIE (Deep Reactive ion Etching) process. The cap wafer vias are filled with a conducting material by means of electroplating process. The seed metal is usually an UBM (Under bump metallization) layer which is subsequently pattemed to form bond pads on both top and bottom wafers. These two wafers are then aligned and bonded with soldedmetal to form a hermetically sealed wafer level package. Altemate methods are also investigated for plugging the via holes with conducting material and the process has been explained.

A CMOS compatible single resist layer lift-off process for forming patterns on a substrate is described. Unlike in most other methods, an ion bombardment is employed here to harden the top of the resist leaving the sidewall of the resist unaffected. The resist is then treated to a low temperature O 2 plasma etching process to achieve a T-shaped undercut profile. This process is found to be simple, repeatable and controllable. Resist profile with adjustable overhang length and the sidewalls of the resist profile with an almost T-shape could be achieved with the help of the process described in the current work. Such increased overhang length prevents metallization of the sidewalls of the resist, and thus facilitates more rapid removal of the resist during lift-off. The process starts from a patterned resist layer having vertical resist profile. It is then subjected to Ion bombardment to harden the top surface of the resist leaving the sidewalls unaffected. The ions are directed at sufficient dose and energy to cause the top of the resist mask to get hardened. Subsequently, the resist patterns are subjected to a low temperature isotropic plasma etching process resulting in an under-cut T-shaped resist profile. This process is highly suitable for MEMS application where metals like Cr, Au, Cu etc are frequently used but are difficult to dry etch.

We report here the magnetization and Eu151 Mossbauer studies in ordered perovskite-type oxides, Ba2EuRu1−xCuxO6 (x=0.0, 0.1 and 0.2). The parent compound, Ba2EuRuO6, shows a magnetic ordering at 40K. Both the magnetization and Mossbauer measurements indicate that the magnetic ordering temperature is unchanged as Cu partially substitutes Ru. Despite the fact that the ground state of Eu3+ is a nonmagnetic J=0 state, the Eu151 Mossbauer resonance spectrum shows a clear splitting into six lines for T

This study demonstrates precise profile control of 3D lateral junction traps in silicon by exploiting a 2D mask layout and isotropic etching. The traps penetrate through silicon partitions and laterally link microfluidic channels. Since the trap constrictions cannot be registered directly by planar lithography, they are not trivial to define but critical for capturing cells in suspension. A special mask layout introduced here when combined with isotropic etching can form elliptic and circular constrictions. The mask layout offers three design parameters: two geometric angles and a separation distance between them. The design parameters have been systematically varied and a set of corresponding trap structures have been fabricated. Mapping of the constriction profiles to design parameters indicates that the constriction shape is mainly determined by the two design angles whereas the constriction size is controlled by the separation distance and total isotropic etching. It is shown that a circular constriction can be fabricated by setting the two angles such that their harmonic mean yields a critical value of about 45°. The constriction size may vary from several micrometers to tenths of micrometers depending on the separation distance and isotropically etched amount.