Search

The control of global critical dimension uniformity (GCDU) across the entire mask becomes an important factor for the high-end masks quality. Three major proceses induce GCDU error before after-developing inspection (ADI) including the E-Beam writing, baking, and developing processes. Due to the charging effect, the fogging effect, the vacuum effect and other not-well-known effects, the E-Beam writing process suffers from some consistent GCDU errors. Specifically, the chemical amplified resist (CAR) induces the GCDU error from improper baking. This phenomenon becomes worse with negative CARs. The developing process is also a source of the GCDU error usually appears radially. This paper reports the results of the study of the impact of the global CD uniformity on mask to wafer images. It also proposes solutions to achieve better masks.

Negative-tone chemically amplified resists (nCARs), like NEB22 are promising candidates for next-generation lithography, e.g. 90 nm and 65 nm technology node and next-generation lithography. For these resists, e-beam exposure and post-exposure bake (PEB) are most critical processes, since these resists show a strong sensitivity to post-exposure delay (PED) in vacuum during e-beam writing of about 0.5 nm/h, and in air while waiting for PEB. Further, such resists show a strong PEB temperature sensitivity of up to 8 nm/K. The multi-zone hotplate approach of the APB AFB 5500 bake system with its use prior temperature uniformity results in excellent global CD-uniformity already. However, all kinds of systematic large area effects of processes, e.g. blank coat/bake, exposure, PED, the PEB itself, etch loading, etc. may transfer in additional systematic CD-errors. Such systematic, repeatable errors can be reduced during PEB by superimposing an appropriate non-uniform temperature profile onto the regular, optimized uniform bake temperature profile, thereby compensating for such CD-non-uniformities. The required temperature profile can automatically be calculated from a suitable gobal CD measurement, determined in a typical process flow. The compensation of CD-errors resulting from vacuum PED and hotplate temperature characteristics is demonstrated here, by using automated temperature profile calculation. The global CD uniformity was improved significantly, the achieved results show a typical reduction of about 20-30%, from a total global range of about 9nm to about 6-7nm on leading-edge production photomasks.

The specifications of mask critical dimension (CD) have become much tighter for sub-100nm nodes to satisfy wafer CD uniformity requirements. The small patterns produced by aggressive optical proximity correction compound the difficulty, thereby necessitating the use of e-beam writers in combination with chemical amplified resists (CARs). Challenges of resists include post coating delay (PCD), post exposure delay (PED) in vacuum, and strong post exposure bake (PEB) sensitivity. CD errors are classified into localized area and global ones; machines causing each type of errors are then identified. Focus variation and fogging effect have to be emphasized for the 65-nm requirements. Although the DOF of e-beam systems is larger than that of the optical systems, high current density and/or plate-to-plate deviation may cause focus variation to result in poor CD uniformity. Therefore, dosage optimization is necessary for getting the best focus. The fogging effective level is around 3~10 nm at various pattern loadings. The paper presents, quantitative results and the methodology leading to them. Key words: L-CD, G-CD, PCD, PEDV, PEB sensitivity, E-beam, DOF, Fogging effect 1. INTRODUCTION The optical lithography process is approaching the 65-nm node and beyond, and the requirements for CD on mask have become stricter than ever. For example, according to the latest ITRS2002 mask requirements, CD uniformity of 2.5 nm (3-sigma) for isolated lines and 4.2 nm (3-sigma) for dense lines will be required for 65-nm node binary intensity masks in 2007. However, current CD-SEM measurement precision is greater than 3 nm, about 3 times larger than the estimated local CD (L-CD) error components of the e-beam writer alone. Substrate charging is the fundamental limitation on extending CD-SEM metrology needed for meeting CD control requirements. Timely development of novel mask-making-specific non-SEM metrology and tooling for the 65-nm technology node seems to be an inevitable trend. [1] To meet these strict error requirements, pattern CD errors induced by process should be thoroughly examined, and as many of them should be reduced. Among the many factors that affect pattern CD accuracy, the variation of

The multizone hotplate approach of the APB5500 bake system achieves temperature uniformity significantly superior to conventional bake tools, resulting in unmatched global critical dimension (CD) uniformity from the postexposure bake (PEB) process. Progress toward 65-nm next-generation lithography, however, requires the application of negative-tone chemically amplified resists (nCARs) like NEB22. This nCAR is characterized to show a strong sensitivity to postexposure delay (PED) in vacuum during electron-beam writing of 0.5 nm/h, and also a strong PEB sensitivity of 7.8 nm/°C, both resulting in systematic CD errors. These CD errors are compensated with the APB5500 bake system during PEB by automatically applying an appropriate nonuniform temperature profile. This temperature profile is calculated by an algorithm considering the resist and mask heat transfer properties. A CD uniformity improvement from 8.9 to 6.7 nm total range (25%) on a state of the art production mask is achieved.