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In this paper, a Feedback-MOS (FB-MOS) structure with C-SenseFET (FMC-SenseFET) is proposed. The FB-MOS region is connected to the Sense terminal of the C-SenseFET by the gate-drain short (diode) connection, which provides negative bias for the G2 terminal. When the temperature changes, the positive temperature characteristic of FB-MOS provides negative feedback for the current drift caused by the J-FET region, while the negative bias will change the width of the depletion layer in the J-FET region, which could further suppress the current drift. Compared with normal structure, the M (Current drift coefficient with temperature) of the charging current in the saturated region can be reduced by 53.8%, besides that, the proposed structure can generate a zero current drifting point at various temperatures in the linear region where the sampling function is realized, which could improve the temperature stability of C-SenseFET in two operating modes.

The thermal resistance of the power VDMOS device is an important parameter reflecting its thermal characteristics and reliability. The solder layer is one of the most important component which has a great influence on the thermal resistance. In this paper, three different power VDMOS in ITO-220 package are used as samples to analyze the relationship between the thickness of the solder layer and the thermal resistance. Through the results of finite element simulation and experiment, it is concluded that the thermal resistance is approximately linear with the thickness of solder layer.