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A high output voltage charge pump circuit utilizing vertical parallel plate (VPP) capacitors to boost voltage is proposed. With comparable capacitance density, the designed VPP capacitor owns a breakdown voltage much higher than that of metal-insulator-metal (MIM) capacitor. Thus, the output voltage and chip size of charge pump circuits are not limited by the pumping capacitors. To further improve the voltage pumping gain, the threshold voltage and the body effect coefficient of MOSFETs are removed by applying dynamic control to both the charge transfer switches (CTS's) and the MOSFETs' body voltages.

A GaAs Planar Schottky Barrier Diode (PSBD) with Schottky contact radium of 1μm has been fabricated using Electron Beam Lithography method. The measured ideality factor, reverse current, series resistance, junction capacitance and the cut-off frequency of the PSBD are ∼1.29, ∼150 fA, ∼3 A, ∼11 fF and ∼4.8 THz, respectively. A 340GHz 4× sub-harmonic mixer (SHM) chip was designed using the proposed GaAs PSBD. The 4× SHM was measured through on-wafer testing. With LO frequency of 85 GHz, the measured conversion loss of ∼51 dB was obtained. The 4× SHM chip occupies 600μm∗ 970μm including the testing pads.

The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, V t -roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage ( V t ) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing V t at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLSI applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability.

A two-port capacitorless PNPN device with high density, high speed and low power memory fabricated using standard CMOS technology is presented. Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed (ns level), large read current margin (read current ratio of 104×), low process variation, good thermal reliability and available retention time (190 ms). Furthermore, the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.