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Carbon nanotube field effect transistor (CN-MOSFET) is attractive for the realization of future monolithic three-dimensional (M3D) memory circuits with ultra-high integration density, capacity, efficiency, and speed. However, the yield of each vertically-stacked active layer can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) caused by process imperfections. The potential integration density benefits of M3D circuits also may not be fully realized by the large area skews between different layers within standard cells. In this paper, ultra-high density and robust M3D static random-access memory (SRAM) cells are proposed for tolerance to the removal of m-CNs. By minimizing the skew and area of each device layer, the 16Kibit memory arrays with the proposed SRAM cells enhance the integration density by up to 82.92% as compared to the carbon-based traditional 2D and previously published M3D memory arrays. While achieving high functional yield and maintaining robust read/write operations, the proposed SRAM circuits enhance the overall electrical quality by up to 27.41x as compared to the alternative 2D and M3D memory arrays.

Leakage power consumption of clock distribution networks (CDNs) is an important challenge in modern synchronous integrated circuits with billions of deeply scaled transistors. Multithreshold CMOS technology is commonly used to provide power reduction in standby mode while maintaining high performance in active mode. In this paper, a novel dual-threshold-voltage repeater circuit with split inputs–outputs (SPLIT-IOs) is employed for suppressing leakage currents in gated CDNs. Three floor planning strategies are considered for clock distribution across the chip with signal transition times of less than or equal to 50 ps at the leaves. Depending on the power supply voltage and floor plan, the standby leakage power consumption is reduced by 50.36%–78.43% with the proposed clock tree with SPLIT-IO repeaters as compared to the conventional three-level H-tree in a 45-nm CMOS technology. The spread of standby leakage power due to process variations is compressed by 36.72%–73.77% with the proposed clock tree as compared to the standard network. The proposed circuit technique significantly lowers the total energy consumption of partially active networks with local clock gating as well. The energy savings provided by the SPLIT-IO buffers are enhanced with the scaling of power supply voltage and frequency in synchronous systems-on-chip.

The yield and robustness of carbon-based embedded memory can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) that create short circuits in the channel arrays of CN-MOSFETs. The malfunction caused by these short circuits can be avoided by removing the m-CNs using specialized etching techniques. During the removal of metallic nanotubes, however, residual m-CNs may be left in the channel arrays of some of the transistors. Furthermore, all of the nanotubes may be etched in some of the channel arrays, thereby causing permanent open circuits and malfunction. A statistical design methodology that considers all of these possibilities related to the formation and removal of metallic nanotubes is needed for achieving functional memory circuits with high yield despite fabrication imperfections in carbon-based electronics. An m-CN-removal-tolerant high-yield six-transistor (6T) static random access memory (SRAM) cell is proposed in this paper considering the nonidealities of CN-MOSFET fabrication. A general statistical functional yield model of memory arrays with 6T SRAM cells is developed by comprehensively considering the spatial correlations among different transistors. The yield of the m-CN-removal-tolerant memory array is increased by 131 times, and read access speed is enhanced by 16.42% as compared with the standard design that does not provide any tolerance to the removal of m-CNs in a 16-nm CN transistor technology.

A new variable strength keeper technique is proposed in this paper for achieving robust, high-speed, and low-leakage dynamic logic gates with carbon nanotube transistors. The strength of keeper is dynamically adjusted depending on the logical state of dynamic node during input evaluation phase in a domino logic circuit. While providing similar noise immunity, the evaluation delay and power-delay product of proposed domino circuits are reduced by up to 13.33% and 13.84%, respectively, as compared to standard domino circuits in a 16nm carbon nanotube transistor technology. Furthermore, the proposed domino circuits provide up to 77.98% savings in average leakage power consumption as compared to standard domino logic circuits in idle mode.

Metallic carbon nanotubes (m-CNs) cause malfunction by shorting the source and drain terminals in carbon nanotube transistors. To achieve high-yield with robust read and write operations, a new nine carbon nanotube MOSFET (9-CN-MOSFET) static random-access memory (SRAM) cell that can tolerate the removal of m-CNs is proposed in this paper. A functional yield model considering the spatial correlations of carbon nanotubes in channel arrays of CN-MOSFETs is developed. The yield of the m-CN-removal-tolerant 9-CN-MOSFET SRAM array is increased by $21309{\times }$ as compared to a design that does not consider process imperfections in carbon-based electronics. Due to the increased strength of read and write ports, the read delay and worst-case write delay of the m-CN-removal-tolerant 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit that does not consider process imperfections in a 16-nm CN-MOSFET technology.

In this paper, a robust monolithic three-dimensional (M3D) 4N4P eight carbon nanotube MOSFETs (8-CN-MOSFET) static random-access memory (SRAM) cell is presented for achieving high integration density with tolerance to the removal of metallic carbon nanotubes. While maintaining the high functional yield and robust read/write operations, the layout area of the proposed 16K-bit M3D 4N4P 8-CN-MOSFET SRAM array is reduced by 45.32% and 31.56% as compared to the previously published 2D and M3D 6N2P 8-CN-MOSFET SRAM circuits, respectively.

A new low power clock distribution network with multi-threshold-voltage (multi-V t ) repeaters is presented in this paper. A repeater circuit with two inputs and two outputs is employed for suppressing leakage currents in gated clock distribution networks. The standby leakage power consumption is reduced by 50.93% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 0.8V in a 45nm CMOS technology. In addition to providing significant power savings in idle clock distribution networks, the proposed circuit technique also lowers the total energy consumption of partially active networks. Depending on the percent of segments that experience local clock gating, the total energy consumed by the proposed clock network is 6.78% to 80.43% lower as compared to the conventional clock tree with a power supply voltage of 0.4V and a clock frequency of 10MHz.

International audience; I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades [1] (see Fig. 1 ). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown in Fig. 1 , more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade [2] , [3] . At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown in Fig. 2 , for several systems and system-on-chip subsystems [4] . This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit [5] .

A robust SRAM cell that can tolerate metallic carbon nanotubes is presented in this paper. A statistical yield model of carbon nanotube transistors and memory circuits is developed considering spatial correlations. The yield of the proposed process-imperfections-aware SRAM array is increased by more than twenty-one thousand times as compared to an alternative design that assumes perfect carbon nanotubes in a 16nm technology.

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations. A new asymmetrically ground-gated 7T SRAM circuit.Low leakage high data stability SLEEP mode.Up to 7.03x data stability enhancement during read operations.A specialized write assist circuitry.Enhanced overall quality as compared to industrial standard 6T and 8T SRAM circuits.Highly immune to process parameter fluctuations.

Multi-threshold CMOS (MTCMOS) technique is commonly used for suppressing leakage currents in idle circuits. The application of MTCMOS technique to static random access memory (SRAM) circuits is investigated in this paper. Two asymmetrically ground-gated MTCMOS SRAM circuits are presented for providing a low-leakage SLEEP mode with data retention capability. The read and hold static noise margins are increased by up to 7.24× and 2.39×, respectively, with the new asymmetrical SRAM cells as compared to conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. The overall electrical quality of a memory array is enhanced by up to 103.52× and 57.75% with the proposed asymmetrically ground-gated memory cells as compared to the conventional ground-gated 6T and eight-transistor (8T) SRAM cells, respectively. The new asymmetrical SRAM cells also exhibit enhanced tolerance to process parameter variations and lower minimum applicable power supply voltages as compared with the conventional 6T and 8T SRAM cells.

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09%, while providing similar read speed as compared with the conventional six-transistor (6T) SRAM cell in a 16-nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by $4.57\times $ and $3.90\times $ with the proposed 9-CN-MOSFET SRAM cell as compared with the conventional 6T SRAM cell and a previously published eight-transistor (8T) SRAM cell, respectively. A 1 Kibit SRAM array with the new memory cells consumes 34.18% and 12.27% lower leakage power as compared with the memory arrays with 6T and 8T SRAM cells, respectively, in idle mode. The overall electrical quality is enhanced by up to $13.63\times $ with the proposed 9-CN-MOSFET memory circuit as compared with the other memory cells that are evaluated in this paper.

A high-yield nine carbon nanotube MOSFET (9-CN-MOSFET) SRAM cell that can tolerate the removal of metallic carbon nanotubes (m-CNs) is proposed in this paper. A functional yield model of carbon nanotube transistors and memory circuits is developed considering the spatial correlations of CNs in the channel arrays. The yield of the m-CN-removal-tolerant 9-CN-MOSFET SRAM array is increased by 21309x as compared to the previously published memory circuit that does not consider process imperfections. The read delay and worst-case write delay of the proposed 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit in a 16nm CN-MOSFET technology.

Switching speed, active power consumption, standby leakage current, and silicon area are major concerns in buffer design. A new Skewed-IO cell with two split inputs and two split outputs is proposed for low-leakage and high-speed buffer design in this paper. The triple-threshold-voltage buffers with the new Skewed-IO cells offer up to 68.3% and 13.2% reduction in standby leakage currents and propagation delay, respectively, as compared to the conventional static CMOS inverter based buffers under identical load capacitance conditions in a TSMC 65 nm CMOS technology.

Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing power supply voltage in scaled CMOS technologies. A seven-transistor (7T), an eight-transistor (8T), a nine-transistor (9T), and 3 conventional six-transistor (6T) memory circuits are characterized for layout area, data stability, write voltage margin, data access speed, active power consumption, idle mode leakage currents, and minimum power supply voltage in this paper. A comprehensive electrical performance metric is evaluated to compare the memory cells considering process parameter and supply voltage fluctuations. The triple-threshold-voltage 8T and 9T SRAM cells provide up to 2.5× stronger data stability and 765.9× higher overall electrical quality as compared to the traditional 6T SRAM cells in a TSMC 65 nm CMOS technology.

Low-power, compact, and high-performance NP dynamic CMOS circuits are presented in this paper assuming a 16 nm carbon nanotube transistor technology. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated based on HSPICE simulation with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MOSFET (CN-MOSFET) domino logic, and CN-MOSFET NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS adder is reduced by 35.53%, 77.96%, and 15.52% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino adders, respectively. Miniaturization of the CN-MOSFET NP dynamic CMOS circuit reduces the dynamic switching power consumption by 80.54%, 95.57%, and 25.66% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino circuits, respectively. Furthermore, the CN-MOSFET NP dynamic CMOS adder provides up to 99.98% savings in leakage power consumption as compared to the other adder circuits that are evaluated in this study.

Multi-threshold CMOS (MTCMOS) is commonly used for suppressing leakage currents in idle integrated circuits. Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in MTCMOS circuits. Sleep signal slew rate modulation techniques for suppressing mode-transition noise are explored in this paper. A triple-phase sleep signal slew rate modulation (TPS) technique with a novel digital sleep signal generator is proposed. Reactivation time, mode-transition energy consumption, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equal-noise constraint. Influences of within-die and die-to-die parameter variations on the reactivation noise, time, and energy consumption of sleep signal slew rate modulated MTCMOS circuits are evaluated with a process imperfections aware robustness metric. The proposed triple-phase sleep signal slew rate modulation technique enhances the tolerance to process parameter fluctuations by up to 183.1× as compared to various alternative MTCMOS noise suppression techniques in a UMC 80-nm CMOS technology.

Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.

A new threshold voltage tuning methodology is explored in this paper to minimize the peak power/ground bouncing noise with smaller sleep transistors in multi-threshold CMOS (MTCMOS) circuits. Different circuit techniques with the threshold voltage tuning strategy lower the activation noise, the activation delay, and the size of the additional sleep transistors by up to 27.76%, 32.66%, and 85.71%, respectively, as compared to a previously published noise-aware MTCMOS circuit with standard zero-body-biased high threshold voltage sleep transistors in a UMC 80-nm CMOS technology.

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new FinFET memory circuits with asymmetrically gate underlap engineered transistors are proposed in this paper for achieving stronger read data stability and lower leakage power consumption. With the proposed asymmetrical six-transistor SRAM cells, read data stability is enhanced by up to 72.2% while maintaining similar write voltage margin and layout area as compared to the conventional symmetrical six-transistor SRAM cells in a 15nm FinFET technology. Furthermore, leakage power consumption is reduced by up to 37.4% with the proposed asymmetrical FinFET SRAM cells as compared to the conventional six-FinFET SRAM cells with symmetrical transistors.

Ground distribution network noise produced during sleep-to-active mode transitions is an important reliability concern in standard multi-threshold CMOS (MTCMOS) circuits. Different noise-aware sequential MTCMOS circuits are explored in this paper. A low-leakage data retention sleep mode is implemented with smaller centralized sleep transistors to suppress the ground bouncing noise produced during reactivation events in sequential MTCMOS circuits. Ground bouncing noise, leakage power consumption, data stability, and area overheads of different sequential MTCMOS circuits are evaluated with a 90-nm CMOS technology. The peak amplitude of ground bouncing noise is reduced by up to 94.16% with the noise-aware MTCMOS techniques as compared to the conventional Mutoh flip-flop. The application space of different data retention MTCMOS circuit techniques is identified with various design metrics in this paper.

Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio (Ion/Ioff). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.

New multi threshold voltage (multi-Vth) brute-force FinFET sequential circuits with independent-gate bias, work-function engineering, and gate-drain/source overlap engineering techniques are presented in this paper. The total active mode power consumption, the clock power, and the average leakage power of the multi-Vth sequential circuits are reduced by up to 55%, 29%, and 53%, respectively, while maintaining similar speed and data stability as compared to the circuits in a single threshold voltage (single-Vth) tied-32 nm-gate FinFET technology. Furthermore, the area is reduced by up to 21% with the new sequential circuits as compared to the circuits with single-Vth tied-gate FinFETs.

Multi-threshold voltage CMOS (MTCMOS) is an effective technique for suppressing the leakage currents in idle circuits. When the conventional MTCMOS technique is directly applied to a sequential circuit however the stored data is lost during the low-leakage sleep mode. Significant energy and timing penalties are suffered to restore the pre-sleep system state at the end of the sleep mode with the conventional MTCMOS circuits. Two new master-slave MTCMOS memory flip-flops are presented in this paper for providing a low-complexity and low-leakage data retention sleep mode. A small size high threshold voltage static memory cell is integrated into an MTCMOS flip-flop to preserve the stored data while drastically reducing the leakage power consumption of idle sequential circuits. The already existing sleep signal of the MTCMOS circuitry is also used for controlling the data retention and restoration operations, thereby eliminating the need for any extra control signals. The memory flip-flops provide a significantly simplified sleep control/data transfer mechanism and reduce the circuit area by up to 37.21% as compared to the previously published MTCMOS flip-flops. Furthermore, the leakage power consumption with the presented techniques is reduced by up to 97.71% as compared to the previously published techniques in a UMC 80 nm CMOS technology.

Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the ground-bouncing-noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual lines to the real ground distribution network during the SLEEP to ACTIVE mode transitions. The dependence of ground bouncing noise on the sleep transistor size and temperature is characterized with different power-gating structures. The peak amplitude of ground bouncing noise is reduced by up to 76.62% with the noise-aware techniques without sacrificing the savings in leakage power consumption as compared with standard MTCMOS circuits in a 90-nm CMOS technology.

Two new clocking methodologies based on supply voltage and frequency scaling are proposed in this paper for lowering the power consumption and the temperature-fluctuation-induced skew without degrading the clock frequency. The clock signal is distributed globally at a scaled supply voltage with a single clock frequency with the first clocking methodology. Alternatively, dual supply voltages and dual signal frequencies are employed with the second methodology that provides enhanced power savings. The optimum supply voltage that minimizes clock skew is 44% lower than the nominal supply voltage in a 0.18 ?m TSMC CMOS technology. Novel multi-threshold voltage level converters and frequency multipliers are employed at the leaves of the clock trees in order to maintain the synchronous system performance. The temperature-fluctuation-induced skew and the power consumption are reduced by up to 80% and 76%, respectively, with the proposed dual supply voltage and dual frequency clock distribution networks as compared to a standard clock tree operating at the nominal supply voltage with a single clock frequency.

A new six transistor (6T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stabilityand the integration densityof FinFET memorycircuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced byutilizing PMOS access transistors. The read stabilityis enhanced byup to 62% while reducing the leakage power byup to 22% as compared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate of each pull-up FinFET of the cross-coupled inverters is permanentlydisabled in order to achieve write-abilitywith minimum sized transistors. The proposed independent-gate FinFET SRAM circuit with P-type data access transistors reduces the idle mode leakage power, the write power, and the cell area byup to 62%, 16.5%, and 25.53%, respectively , as compared to a standard tied-gate FinFET SRAM cell sized for similar data stabilityin a 32 nm FinFET technology .

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32nm FinFET technology.

Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra low-power-supply voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active-mode energy consumption. Temperature-adaptive dynamic supply voltage tuning (TA-DVS) technique is proposed in this paper to reduce the high-temperature energy consumption of ultra low-voltage subthreshold SRAM arrays. Results indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures. The impact of the temperature-adaptive dynamic supply voltage scaling technique on the data stability of the subthreshold SRAM bit-cells is presented. The effectiveness of the TA-DVS technique under process parameter and supply voltage variations is evaluated. An alternative technique based on temperature-adaptive reverse body bias (TA-RBB) to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption characteristics of the two temperature-adaptive voltage tuning techniques are compared.

Employing multiple supply voltages (multi- VDD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The new multi-Vth level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.

Clock distribution network consumes a significant portion of the total chip power since the clock signal has the highest activity factor and drives the largest capacitive load in a synchronous integrated circuit. A new methodology is proposed in this paper for buffer insertion and sizing in an H-tree clock distribution network. The objective of the algorithm is to minimize the total power consumption while satisfying the maximum acceptable clock transition time constraints at the leaves of the clock distribution network for maintaining high performance. The new methodology employs nonuniform buffer insertion and progressive relaxation of the transition time requirements from the leaves to the root of the clock distribution network. The proposed algorithm provides up to 30% savings in the total power consumption without sacrificing clock skew as compared to a standard algorithm with uniform buffer insertion aimed at maintaining uniform transition time constraints at all the nodes of a clock tree in a 180 nm CMOS technology.

Temperature dependent propagation delay characteristics of CMOS circuits will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 32nm CMOS technology is enhanced when the temperature is increased at the nominal supply and threshold voltages. The enhancement of circuit speed provides new opportunities to lower the energy consumed by active circuits at elevated temperatures. Temperature-adaptive supply and threshold voltage tuning techniques are proposed in this paper to reduce the high temperature energy consumption without degrading the clock frequency in the active mode. Results indicate that the energy consumption can be lowered by up to 21% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body-bias exponentially reduces the leakage currents as well as the parasitic junction capacitances of the MOSFETs. The temperature-adaptive threshold voltage tuning through reverse body-bias yields an active mode energy reduction by up to 29.8% as compared to the standard zero-body-biased circuits at high temperatures.

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.

Scaling of the standard single-gate bulk MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage current and enhanced sensitivity to process variations. Multi-gate MOSFET technologies mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. Double-gate FinFET is the most attractive choice among the multi-gate transistor architectures because of the self-alignment of the two gates and the similarity of the fabrication steps to the existing standard CMOS technology. New latches and flip-flops based on independent-gate FinFETs are proposed in this paper to simultaneously reduce the power consumption and the circuit area. With the proposed independently biased double-gate FinFET sequential circuits, the active power consumption, the clock power, the leakage power, and the circuit area are reduced by up to 47%, 32%, 42%, and 20%, respectively, while maintaining similar speed and data stability as compared to the standard sequential circuits with tied-gate FinFETs in a 32-nm FinFET technology.

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.

A design technique based on optimizing the supply voltage for simultaneously achieving energy efficiency and temperature variation insensitive circuit performance is proposed in this paper. The supply voltages that suppress the propagation delay variations when the temperature fluctuates are identified for a diverse set of circuits in 180 and 65nm CMOS technologies. Circuits display temperature variation insensitive propagation delay when operated at a supply voltage 44-47% lower than the nominal supply voltage (V"D"D=1.8V) in a 180nm CMOS technology. Similarly, the optimum supply voltages are 67-68% lower than the nominal supply voltage (V"D"D=1.0V) in a 65nm CMOS technology. At scaled supply voltages, integrated circuits consume lower power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive for low-power applications with relaxed speed requirements. A new design methodology based on threshold voltage optimization for achieving temperature variation insensitive circuit speed is also evaluated. The energy per cycle and the propagation delay at the supply and threshold voltages providing temperature variation insensitive circuit performance, minimum energy-delay product, and minimum energy are compared. Results indicate that low-power operation and temperature variation tolerance can be simultaneously achieved with the proposed techniques.

Leakage power that is consumed by gigascale clock distribution networks is an important challenge in modern synchronous integrated circuits with billions of deeply-scaled transistors. A novel dual-threshold-voltage repeater circuit with split inputs and outputs is employed for achieving enhanced power efficiency in clock distribution networks in this paper. With the new repeaters, the mean of the statistical leakage power consumption distribution is reduced by up to 39.6% without increasing the layout area, active power consumption, clock skew, and clock period as compared to a conventional clock distribution network with standard static CMOS inverter based repeaters in a TSMC 65nm CMOS technology.

A new variable strength keeper technique is presented in this paper for achieving higher-speed and lower-leakage currents in wide fan-in dynamic logic gates with carbon nanotube transistors. The strength of the keeper is dynamically adjusted depending on the logical state of the dynamic node during evaluation phase in a domino logic circuit. While providing similar noise immunity, the evaluation delay and power-delay product of the proposed domino logic circuits are reduced by up to 13.33% and 13.84%, respectively, as compared to the standard domino logic circuits in a 16nm carbon nanotube transistor technology. Furthermore, the proposed technique provides up to 77.98% savings in average leakage power consumption as compared to the standard domino logic circuits in idle mode.

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies

Supply voltage scaling is a commonly used technique for saving energy in microprocessors. The scalability of power supply voltage is limited by the data stability and write ability requirements of SRAM cells in memory cache. Noise margins of memory cells shrink, thereby degrading reliability and causing failure at lower power supply voltages. A triple-threshold-voltage nine-transistor SRAM cell that is capable of reliable operation at ultra-low power supply voltage levels down to 390mV is presented in this paper. While offering comparable or higher data stability, the tri-Vt 9T SRAM array lowers the leakage power consumption, energy per read cycle, and energy per write cycle by up to 94.5%, 22.8%, and 34.5%, respectively, as compared to the conventional 6T SRAM arrays that operate at the nominal VDD = 1.2V in a TSMC 65nm CMOS technology.

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.