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This work analyzes the angular resolution (AR) of the monostatic forward-looking synthetic aperture radar (FL-SAR). A general mathematical expression for the theoretical AR of the FL-SAR is derived. Simulation-based validations show that the proposed expression yields precise ARs for both single input single output FL-SAR (FL-SISO-SAR), and multiple input multiple output FL-SAR (FL-MIMO-SAR) configurations. Moreover, the proposed expression shows compatibility with near-field as well as far-field geometries. Lastly, the proposed expression also covers challenging situations such as FL-MIMO-SAR with largely spaced MIMO arrays and targets at look angles equal or close to zero degree.

Millimeter-wave beamforming transmitters use antenna arrays to increase the EIRP by focusing the radiation pattern into a direction chosen by programming the TX phase shifters. However, under sharp scanning angles, the antennas load each other (see Fig. 26.4.1) such that in each antenna path the load seen by an individual PA in the output matching network (OMN) deviates from the load corresponding to boresight transmission. This situation can be accompanied by other external factors, such as antenna blockage, that increase VSWR. To restore the PA performance under increasing VSWR conditions, one can use a tunable matching network (TMN) that is controlled by the observed VSWR. The latter is then measured by a VSWR sensor, which is presented here. The overhead of such a sensor in terms of form factor, power consumption, and TX performance degradation should be minimal. The sensor described here can measure reflection coefficients with a magnitude of up to 0.7 (corresponding to a VSWR of 5.7) at 28GHz. It detects the complex voltage difference over a 235fF sensing capacitor that is inserted in the signal path at the PA output. The magnitude and phase of this voltage vary with the complex reflection coefficient \Gamma and are detected separately. The loading effect of the rest of the sensor can be modelled as a 32fF shunt capacitor added to the matching network, equivalent to an extra insertion loss of less than 0.2dB.

A 10GHz FMCW subsampling PLL is presented, that uses a low-power charge-integrating QDAC to tune the VCO for wideband low-noise modulation. Nonlinearities in the QDAC modulation path are corrected within 700µsec cold start-up, followed by a full on-chip background calibration engine to track supply and temperature variations. The PLL consumes 11.7mW (of which

Indoor radar applications detecting people, vital signs and minute gestures require a high range resolution. This paper presents a 145GHz FMCW radar transceiver with on-chip antennas in 28nm bulk CMOS. An RF bandwidth of 13GHz yields an 11mm range resolution, and the high RF carrier permits greater velocity and MIMO-angular resolution. An external chirp signal at 16.1GHz is upconverted to 145GHz via a cascade of two frequency triplers in the RX and TX. For MIMO operation, a central chirp signal from a sub-sampling PLL integrated in 28nm CMOS [1] is distributed to multiple TRX chips on a PCB, eliminating mm-wave signal routing. The radar operates over a 0.15-to-10m range using fast sawtooth chirps of 5-to-50 μ {s} duration. The beat frequency at IF fits between 400kHz and 15MHz. The on-chip TX leakage produces a strong beat near DC, suppressed via active highpass filtering. However, group delays of the PA and LNA can shift the beat into the RX passband. This is overcome by delaying the 16.1GHz RX chirp on chip. The chip dissipates 500mW in continuous mode, with the option of a low-power, duty-cycled FM transmission mode (for close ranges) enabled via fast powering built into the transceiver.

This work presents in-pixel circuit techniques for burst-mode ultra-high-speed imagers to improve the noise performance while maintaining a dense analog memory storage for each pixel. Together with an AC coupling CDS stage, in-pixel amplification is demonstrated to be useful to improve effective frame depth for longer recording time. Considering the benefits on scaling and power consumption, a 108-cell memory bank (10fF/cell) is implemented inside the pixel. Two types of pixel variations were fabricated in CMOS 130nm technology. The photon transfer curves of both pixel types are measured over different operation speeds up to 20Mfps showing noise performance of both variations to be less than 10e- noise.

This paper proposes the concept of electrical balance filters to enable integrated, tunable RF filters, where a pass- and stopband are designed by the change in electrical-balance across frequency. These filters can be constructed using low Q integrated LC resonators. The stopband frequency is the frequency where two on chip balance networks are tuned to be equal in impedance or ‘balanced’, while the passband frequency is the frequency where the balance condition is disturbed as much as possible for low insertion loss. A 1.5mm2 electrical balance low-pass filter prototype is implemented in 0.18µm SOI CMOS. It has 60dB, >33MHz stopband tunable from 1.75 to 3.7 GHz.

Millimeter-Wave transceivers with beamforming capabilities, such as the one presented in this work, are a key technology to reach 4 or 6Gb/s at 10m range with the IEEE 802.11ad standard. Moreover, for mm-Wave access in 5G it will also be necessary to boost peak data-rates far beyond 1Gb/s at hundreds of meters in small cells. Transceiver architectures with beamforming often combine superheterodyne with RF beamforming [1], leading to a high power consumption and a suboptimal RX noise figure due to losses in the beamforming circuitry. In contrast, the 57-to-66GHz TRX IC presented in this paper, whose architecture is depicted in Fig. 13.5.1, uses direct conversion and analog baseband beamforming. Direct-conversion radios are inherently simpler than superheterodyne and do not have to cope with the image frequency, but on the other hand they may suffer from pulling of the PA on the VCO. In this work this is avoided by the non-integer ratio of 2.5 between the operating frequency and the 24GHz PLL that subharmonically injection locks a 60GHz quadrature oscillator (Fig. 13.5.2).

An electrical-balance duplexer (EBD) is a tunable RF front-end concept that seeks to address several key challenges of 4G and 5G mobile systems [1]. The basic principle is shown in Fig. 20.8.1. Duplexer isolation is achieved when the signals in paths 1 and 2 cancel and prevent the TX signal from appearing at the RX port. This cancellation is achieved by "balancing" the antenna impedance ZANT with an on-chip tunable impedance ZBAL.

The two-point injection scheme has proven to be an effective technique for overcoming the problem of PLL bandwidth limitations during wideband polar phase modulation. The quality of the phase-modulated signal, typically expressed in terms of error-vector magnitude (EVM), still remains limited by the PLL phase-noise, gain mismatch between the two injection paths and linearity of the digital-to-modulated phase conversion. We present a phase modulator that makes use of an analog, fractional-N, digital-to-time-converter (DTC)-based subsampling PLL that achieves -37.4dB EVM around a 10.24GHz fractional carrier during 10Mb/s GMSK modulation. The subsampling PLL architecture uses no power-consuming divider and allows wide PLL bandwidth (because of its high phase-error detection gain) for optimal VCO noise suppression. The VCO has a secondary, digitally controlled capacitor bank (modulating DAC) used during two-point modulation. The gain errors and nonlinearities in the digital-to-modulated phase conversion are automatically background-calibrated in both injection points: in the phase-error detection path (where nonlinearity is dominated by the DTC INL) and in the VCO modulating capacitor bank (where nonlinearity is dominated by capacitor mismatch and nonlinear capacitance-to-frequency conversion).

IM3 cancellation is a popular technique in LNAs to achieve very high linearity, but is also very sensitive to the exact device (bias) operating point. A 0.7-1.15GHz complementary common-gate LNA in 0.18µm silicon-on-insulator CMOS is presented that achieves good out-of-band (OOB) linearity without IM3 cancellation. Measurements of the 0.9mm2 prototype show a gain of >7dB, an NF of 2.6kV HBM discharge, while the overall circuit is protected for >1kV HBM discharges.

When using electrical-balance duplexers (EBDs) to provide RF self interference cancellation for in band full duplex, in-band distortion produced by nonlinear CMOS switches in the duplexer cause distortion that limits the headroom for additional self interference cancellation in subsequent cancellation schemes in the transceiver. A prototype EBD is fabricated in 0.18µm SOI CMOS to investigate the dynamic range limitations of a transceiver architecture for next generation wireless systems that supports in band full duplex and legacy FDD. Measurements show -85dBm in band distortion at +10dBm TX input power, enough for short-range links at 10MHz BW.

Driven by increasing data-rates, advanced mobile communication systems impose stringent requirements on every transmitter design aspect. Especially when the inter-stage SAW filter is removed, FDD operation using high-order modulation schemes (as in e.g. WCDMA, LTE) demands both remarkable noise performance and linearity, which is difficult to achieve without sacrificing power consumption. On the other hand, the increased switching speed of nanoscale MOS transistors has enabled the implementation of various digital-intensive TX architectures [1-5], that improved system robustness and reduced power and area consumption even in face of decreased supply voltages. However, in these cases reconstruction filtering is hindered by direct digital-to-RF conversion, leading to increased quantization noise and strong sampling aliases. Often addressed by increasing the converter resolution [2,3,4,6] and/or sampling frequency [2], these solutions typically become rather costly and directly affect the overall power consumption. This work introduces a TX architecture that innovates by operating in the charge domain. Its incremental — rather than absolute — signaling improves both quantization noise performance and power consumption. Using a 128MS/S 10b DAC configuration, it achieves −155dBc/Hz at 45MHz offset from a 1GHz modulated carrier, with intrinsic sampling alias attenuation.

A Discrete-Time (DT) analog baseband for Software-Defined-Radio (SDR) receivers is presented. A zero-IF baseband signal at the input of a programmable gm is converted to current, which is integrated on a 5th order DT IIR filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier which integrates freely selectable samples to implement active FIR filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved 10b ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype achieves +10 dBm IIP3, 2 nV/VHz IRN and 52 dB gain range while consuming a maximum power of 15 mW.

The demand for inexpensive and ubiquitous accurate motion-detection sensors for road safety, smart homes and robotics justifies the interest in single-chip mm-Wave radars: a high carrier frequency allows for a high angular resolution in a compact multi-antenna system and a wide bandwidth allows fora high depth resolution. With the objective of single-chip radar systems, CMOS is the natural candidate to replace SiGe as a leading technology [1-6].

This paper presents an integrated phase shifter based on electrical-balance operation. The phase shift of the circuit is set through the difference in impedance between two on chip tunable impedances. Each impedance consists of a parallel combination of a tunable resistor and a tunable capacitor. Measurements of the inductorless, 0.12mm2 prototype implemented in 0.18µm CMOS show a tunable range of >360° of phase shift across 0.5-1.15GHz with >12-bit tuning accuracy, while the 15 to 40dB insertion loss is acceptable for the target application of auxiliary self interference cancellation loops in in band full-duplex capable transceivers. The phase shifter has maximum phase/gain errors of 0.42° and 0.27dB per MHz, respectively.

Mainstream foundries are leaping toward 14nm node and beyond. Although aggressive scaling can substantially improve digital circuit, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Illustrated with a variety of transceivers representing emerging architectures designed for different sub-6Ghz and 60Ghz communication systems, we will depict key challenges that we experienced in our design and optimization process with 40nm and 28nm technology nodes.

In this paper we demonstrates a 79GHz phase-modulated CW radar transmitter in 28nm CMOS. The circuit architecture uses digital pseudo-random noise modulation at a 4GHz RF bandwidth for a low-power implementation with 10.4% power efficiency.

This paper presents a 79GHz fifth subharmonic injection locked oscillator (ILO). Compared to classical ILOs which are based on the nonlinearity of coupling transistors, this work uses inverter chains for input pulse pre-shaping. Thanks to the harmonic rich square wave, the new ILO combines linear and nonlinear mechanisms which together widen the locking range. A prototype chip is fabricated in 28nm CMOS technology. A locking range from 72 to 83GHz is measured under -2dBm input power. The power consumption of the inverter chain, the core circuit and the output buffer is 9mA, 10mA and 9mA respectively. Besides, a peak detector is implemented to ensure the locked ILO operates near the free-running frequency where the output amplitude is higher.

A low-power analog baseband section suitable for 60-GHz receivers using orthogonal frequency-division multiplexing (OFDM) with 16 quadrature amplitude modulation (16-QAM) modulation is presented in this paper. Power efficiency is achieved by combining active-RC with source-follower-based topologies in order to synthesize a custom sixth-order transfer function. The complete chain consists of the cascade of a first-order transimpedance amplifier with finely programmable gain, a fourth-order source-follower-based filter, and a coarse gain first-order programmable gain amplifier. The prototype is implemented in 90-nm CMOS. It achieves a 1-GHz cutoff frequency and programmable gain from 0 to 20 dB with 1-dB step control, drawing 9.5 mA (0-9 dB gain range) or 10.8 mA (10-20 dB gain range) from a 1-V supply. An 8.2-dBm third-order input intercept point and a -145-dBm/Hz input-referred noise power density are measured at 0- and 20-dB gain, respectively. The entire circuit occupies an area of 400 × 390 μm2.

This paper presents a 40nm CMOS transformer based dual-band VCO with differential hybrid coupler for I/Q generation. The average phase noise of the combination over the 54 to 69.3GHz tuning range is -90dBc/Hz at 1MHz offset while the best FOM value is 177dB. Along the wide tuning range, the I/Q mismatch of the hybrid coupler is less than 3 degree. The area of the hybrid is only 60um*65um.

These tutorials discuss the following: Basics of 60GHz LNA and PA Design in CMOS; High-Bandwidth Memory Interface Design; Energy Harvesters and Energy Processing Circuits; Circuit Design using FinFETs; Simulation Techniques for Data Converter Design; On-Chip Voltage and Timing Diagnostic Circuits; SoC Design Methodology for Improved Robustness; Wireless Transceiver System Design for Modern Communication Standards; Design of Voltage References; Data and Power Telemetry for Implants.

This paper presents a charge-domain SAR ADC which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors for passive amplification, without compromising linearity. The prototype in 40nm LP CMOS consists of a 1.1-17.6mS transconductor, combined with a 10b 0-80MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45mA from a 1.1V supply.

A direct-conversion transceiver in 40nm digital LP CMOS for 57-66GHz wireless communication is described. In TX mode the IC consumes 185mW with 10.2dBm P1dB. In RX mode consumption is 130mW with a NF of 5.5dB and 30dB gain. The frequency generation uses a subharmonically injection-locked QVCO with 8GHz locking range over the 57-66GHz band. ESD robustness is more than 4kV HBM. The transceiver achieves -17dB EVM for QAM16 modulation in the 4 channels specified by IEEE 802.15.3c standard.

This tutorial aims to demystify the nonlinear distortion analysis of circuits and systems. Combining the capabilities of analyzing large circuits through simulation-based methods, and the analytical insight provided by symbolic methods, enables the analysis of the nonlinear behavior of complex systems. The simulation-based methods make it possible to pinpoint the dominant nonlinearities, while the symbolic method can be used afterwards to get analytical insight into the nonlinear behavior. Both methods will be demonstrated using a large set of practical examples. The tutorial first introduces the necessary notions on Volterra theory, starting from classical linear system theory. The analytical expressions provided by Volterra theory result in a better understanding of the behavior of the system. The complexity of the resulting expressions, however, limits this technique to simple systems. Second, the tutorial introduces the Best-Linear-Approximation (BLA) paradigm, which represents the nonlinear system as alinear transfer function and an additive nonlinear distortion component. It enables the separation of the various linear and nonlinear contributions and is able to pinpoint the dominant nonlinear distortions in a complex system in a hierarchical way. The main drawback of the simulation-based methods is, however, the reduced analytical insight. Finally, the power of both methods is combined to study a large set of application examples. Starting from a single-transistor circuit, the circuits' complexity gradually increases over OPAMPs to active filters, receiver front-ends, and sigma-delta modulators. Both the symbolic method and the simulation-based method are used side-by-side to gain insight in the nonlinear distortion properties of the systems. All results are finally cross-checked and compared with results available in the literature. During the course, the simulation data will be distributed to the attendees in MATLAB data format so they can get familiar with proposed techniques using MATLAB or Octave examples.

In the future, mobile devices will have more and more access to all kinds of communications and multimedia services. They will have access not only to mobile-phone networks and the mobile Internet, but also to global-positioning systems, broadcasting services, WLAN (wireless-local-area-network) services, short-range connectivity, and many others. These future devices will also function in all kinds of situations - at home, in the office, during travel, and so on. ICs for these future mass-market wireless-communication consumer applications will be competitive only when they become small, energy efficient, and cost-effective.

MM-Wave technology has been rapidly evolving and is characterized with a plethora of benefits for several applications such as: broadband communication, automotive radars, imaging, and radio astronomy systems. This workshop highlights recent advancements and discusses the challenges in mm-Wave applications and systems. Active as well as passive mm-wave systems will be covered. This particular presentation focuses on CMOS radio architectures that realize beamforming.

Ultra deep submicron CMOS has reached a speed that allows handling of mm-wave signals and in addition, it allows to make digital circuitry very compact. For example, 1 mm^2 can contain 1 million gates in 45nm CMOS. These advantages can be exploited to design complex single-chip transceivers operating at 60 GHz, where a 7 GHz band is available for high-datarate applications. In the coming years we will see several applications operating around 60 GHz, such as wireless HDMI, short-range sync&go and wireless docking stations. To compensate the high path loss of wireless transmission at 60 GHz, one can make use of phased antenna arrays, which can be made compact at those high frequencies. The use of phased arrays requires electronic beam steering. The elaboration of beamforming architectures in CMOS transceivers together with the design of mm-wave building blocks and very wideband analog baseband circuits is the subject of intensive research nowadays. This presentation discusses the design of mm-wave transceivers in ultra deep submicron CMOS for high datarate mm-wave wireless applications. The design of complete architectures will be discussed, together with the design of individual building blocks such beamforming circuits, frequency synthesizers and classical transceiver functions operating around 60 GHz.

Charged device model (CDM) electrostatic discharge (ESD) stress is a major concern for inductor-based ESD protection strategies for RF circuits processed in advanced nano-CMOS technologies. The CDM robustness of such protection methodology is investigated in this paper based on very-fast transmission line pulse (VFTLP) measurements. Its applicability is discussed for future technologies and RF applications.

Modern integrated radio systems require highly linear analog/RF circuits. Two-tone simulations are commonly used to study a circuit's nonlinear behavior. Very often, however, this approach suffers limited insight. To gain insight into nonlinear behavior, we use a multisine analysis methodology to locate the main nonlinear components (e.g. transistors) both for weakly and strongly nonlinear behavior. Under weakly nonlinear conditions, selective Volterra analysis is used to further determine the most important nonlinearities of the main nonlinear components. As shown with an example of a 90 nm CMOS wideband low-noise amplifier, the insights obtained with this approach can be used to reduce nonlinear circuit behavior, in this case with 10 dB. The approach is valid for wideband and thus practical excitation signals, and is easily applicable both to simple and complex circuits.

Scaling to 45 nm node and below might necessitate the use of new processing steps (e.g. new gate stacks) or new device concepts such as FinFETs. Although intrinsic transistor speed increases with scaling, some analog performance parameters tend to degrade. In this paper we show with experimental results and simulations on analog and RF circuits that for high-speed and RF applications, downscaling to 45 nm channel length of bulk devices still improves RF circuit performance, while for low-frequency, high-gain applications FinFET technology offers better circuit performance than planar bulk CMOS.

Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as 'plug-and-play',is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.

It has been known that using selective epitaxial growth (SEG) silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency ( max) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on dc C and RF performance of NMOS transistors. Up to a 28%–45% improvement in max is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain ( S/D) architecture. The maximum transconductance ( ) of the S/D device reaches a value of 1100 mS/mm, which in turn gives a very high of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.

Communications based on beamforming concept require the design of complexsystems using a large number of radio frequency (RF) front-end modules. For theefficient performance of the system, each element must be able to be in its optimalworking zone, which must also be the case for the power amplifier (PA) whose linearity and power depend on the output matching. The amplifier's load impedance, which corresponds to one of the radiating elements of the antenna array, can vary according to its environment (VSWR) and deteriorate the overall performance of the system. In the end, the signal distributed on each antenna to form the global beam must be controlled in phase and amplitude to guarantee the quality of the communication.In this context, the thesis works are related to the new topologies’ research, asthe development of elementary blocks, to create a new power amplifier architecturewhich will be robust to its environment variations. One of the main challenges iscontrolling the phase of the PA and maintaining its RF performances according to themanufacturing process (PVT) variations. Another challenge is to achieve high efficiency PA, while maintaining very good linearity, which is a break with the traditional high efficiency/good linearity trade. In such conditions, the phase control of the PA is a major advantage.A first step in his work consists in proposing a global approach to the PA designin its environment and thus quantifying the impact of the phased-array antennaimpedance variations on the power amplifier RF performances (gain, phase shift). Once the sensitive points have been identified, several PA architectures have been considered to address the problem (s).A first solution with a stand-alone PA improves the robustness against the VSWRantenna variations. Several PA topologies derived from this solution then do it possibleto address the new problems of phase control and fine-tuning of the operatingfrequency. These PA architectures integrating the new concepts developed during thisthesis were implemented in 130nm SiGe and 65nm CMOS-SOI technologies fromSTMicroelectronics. The measurement results validate the architecture of the selfcontained PA with the operating frequency fine-tuning and the phase/voltage detection.This design approach is not limited to 5G communications and can be easilyextended to other frequencies and for other applications such as satellitecommunications (SATCOM). It is not dependent on the silicon technology choice and can be used for other RF circuits such as low noise amplifiers., Les communications basées sur le principe du beamforming imposent de concevoirdes systèmes complexes utilisant un grand nombre de frontaux radiofréquences (RF). Pour le bon fonctionnement du système, chaque élément doit pouvoir être dans sa zone optimale de travail, ce qui doit être aussi le cas pour l’amplificateur de puissance (PA) dont la linéarité et la puissance dépendent de l’adaptation de sortie. L’impédance de charge de l’amplificateur, qui correspond à un des éléments rayonnants du réseau d’antennes, peut subir des variations en fonction de son environnement (TOS) et détériorer les performances globales du système. Au final, le signal distribué sur chaque antenne pour former le faisceau global doit être contrôlé et maîtrisé en phase et en amplitude pour garantir une bonne communication.Les travaux de thèse se situent dans ce contexte et portent sur la recherche denouvelles topologies, ainsi que l’élaboration de blocs élémentaires, pour créer une nouvelle architecture d’amplificateur de puissance robuste à son environnement. L'un des principaux défis est le contrôle de la phase du PA et le maintien de ses performances RF en fonction des variations du processus de fabrication (PVT). Un autre défi consiste à réaliser un PA à haute efficacité, tout en maintenant une très bonne linéarité, ce qui constitue une rupture vis-à-vis du traditionnel compromis à trouver entre le haut rendement et la grande linéarité. Dans de telles conditions, le contrôle de phase du PA constitue un avantage majeur.Une première étape de ses travaux a consisté à proposer une approche globale de laconception du PA dans son environnement et ainsi quantifier l’impact des variations de l’impédance de charge du PA sur ses performances RF (gain, déphasage) en présence d’un réseau d’antennes. Une fois les points sensibles identifiés, plusieurs architectures de PA ont été envisagées pour adresser le ou les problèmes.Une première solution avec un PA autonome a permis d’améliorer la protection vis-àvis des variations de TOS d’antenne. Plusieurs topologies de PA dérivées de cette solution ont ensuite permis d’adresser les nouvelles problématiques de contrôle de la phase et de l’ajustement de la fréquence de fonctionnement. Ces architectures de PA intégrant les nouveaux concepts développés au cours de la thèse ont été implémentées dans les technologies 130nm SiGe et 65nm CMOS-SOI de STMicroelectronics. Les résultats de mesure ont permis de valider l’architecture du PA autonome avec l’ajustement de la fréquence de fonctionnement et la détection de phase et de tension.Cette approche de conception ne se limite pas aux communications 5G et peut êtrefacilement étendue à d'autres fréquences et pour d’autres applications telles que les télécommunications par satellites (SATCOM). Elle n’est pas dépendante du choix de la technologie silicium et peut être utilisée pour d’autres circuits RF tels que les amplificateurs faible bruit.

The 5G future mobile network is planned to be deployed from 2020, in a context of exponential mobile market and exchanged data volume evolution. The 5G will leverage revolutionary applications for the advent of the connected world. For this purpose, several network specifications are expected notably low latency, reduced power consumption and high data-rates even if no standard is yet defined. The frequency bands traditionally used for mobile networks will not permit the needed performances and several mmW frequency bands are under study to create a complementary frequency spectrum. However, these mmW frequency bands suffer from large attenuation inbuilding material and in free-space. Therefore, several techniques will be implemented to tackle these limitations indense urban areas like backhauling, FD-MIMO and beamforming phased array. This is leading to a large number of transceivers for base stations and end-user devices. CMOS technology offers undeniable advantages for this mass market while FD-SOI technology offers additional features and performances. The power amplifier is the most critical block to design in a transceiver and is also the most power consuming. To address the 5G challenges, several specifications concerning power consumption, linearity and efficiency are expected. The environment variations inbeamforming phased array and the industrial context drive the need for robust topologies while power amplifier reconfigurability is benefic in a context of adaptive circuits. This thesis addresses these challenges by exploring the conception of a robust and reconfigurable power amplifier targeting 5G applications while integrating specific design techniques and taking advantage of 28nm FD-SOI CMOS technology features for reconfigurability purposes., Le futur réseau mobile 5G est prévu pour être déployé à partir de 2020, dans un contexte d’évolution exponentielle du marché de la téléphonie mobile et du volume de données échangées. La 5G servira de levier à des applications révolutionnaires qui permettront l’émergence du monde connecté. Dans ce but, plusieurs spécifications pour le réseau sont attendues même si aucun standard n’est encore défini et notamment une faible latence, une consommation d’énergie réduite et un haut débit de données. Les bandes de fréquences traditionnellement utilisées dans les réseaux mobiles ne permettront pas d’atteindre les performances visées et plusieurs bandes de fréquences millimétriques sont à l’étude pour créer un spectre complémentaire. Cependant, ces bandes de fréquence millimétriques souffrent d’une forte atténuation dans l’air et dans les matériaux de construction. Plusieurs techniques vont être implémentées pour outrepasser ces limitations dans les zones urbaines denses comme le backhauling, FD-MIMO et beamforming phased array. Ces techniques entraînent l’utilisation d’un grand nombre de transmetteurs dans les stations de bases et dans les dispositifs de l’utilisateur final. La technologie CMOS offre d’indéniables avantages pour ce marché de masse tandis que la technologie FD-SOI offre des performances et fonctionnalités additionnelles. L’amplificateur de puissance est le bloc le plus critique à concevoir dans un transmetteur et consomme le plus d’énergie. Afin d’adresser les challenges de la 5G, plusieurs spécifications concernant la puissance consommée, la linéarité et le rendement sont attendues. Les variations de l’environnement dans les beamforming phased array et le contexte industriel nécessitent des topologies robustes alors qu’une reconfigurabilité au niveau de l’amplificateur de puissance est bénéfique dans le cas de circuits adaptatifs. Cette thèse adresse ces challenges en explorant la conception d’un amplificateur de puissance reconfigurable et robuste pour des applications 5G en intégrant des techniques de design spécifiques et en mettant en avant les avantages de la technologie 28nm FD-SOI pour la reconfigurabilité.

A low-power analog baseband section suitable for 60-GHz receivers using orthogonal frequency-division multiplexing (OFDM) with 16 quadrature amplitude modulation (16-QAM) modulation is presented in this paper. Power efficiency is achieved by combining active-RC with source-follower-based topologies in order to synthesize a custom sixth-order transfer function. The complete chain consists of the cascade of a first-order transimpedance amplifier with finely programmable gain, a fourth-order source-follower-based filter, and a coarse gain first-order programmable gain amplifier. The prototype is implemented in 90-nm CMOS. It achieves a 1-GHz cutoff frequency and programmable gain from 0 to 20 dB with 1-dB step control, drawing 9.5 mA (0-9 dB gain range) or 10.8 mA (10-20 dB gain range) from a 1-V supply. An 8.2-dBm third-order input intercept point and a -145-dBm/Hz input-referred noise power density are measured at 0- and 20-dB gain, respectively. The entire circuit occupies an area of 400 × 390 μm2. © 2014 IEEE.

State-of-the art electronic systems include ever more features and gather mixed-signal subsystems, possibly from different physical domains. At the same time, cost and development time are reduced; stressing the need for an efficient design flow for fast and reliable design. The present thesis contributes to the construction of an improved design flow supported by mixed-signal hardware description languages (HDL-AMS). In a hierarchical view, the electronic systems are recursively divided into subsystems, down to basic cells and transistor level. The typical design flow results of a top-down synthesis, from the system specifications to the physical realizations, and of a bottom-up validation, from the test of the basic cells up to the test of the system. To improve the link between the technological level and the basic cells, we develop a measurement-based analog ID card which aims to optimize the analog performance and the reliability at high temperature by enabling the choice of optimal process (bulk vs. partially-depleted silicon-on-insulator (SOI) vs. fully-depleted SOI), optimal devices (e.g. multi-threshold voltages process) and optimal bias (weak vs. moderate vs. strong inversion). In the present thesis, we deal with the following analog performance parameters: gain, gain-bandwidth product, MOSFET mismatch in weak inversion and harmonic distortion of MOSFETs in triode regime. We show that SOI transistors are still advantageous over bulk in deep-submicron CMOS technologies and that short-channel SOI transistors can safely be used for mixed-signal operation up to 250°C. The analog ID card can be included in the design flow supported by HDL-AMS. Behavioral models for the basic cells are developed using such languages and further assembled into a ÄÓ modulator with continuous-time integrators as it is a good candidate for low-power consumption and operation at high temperature. The related design issues are assessed using the behavioral models and a design optimization method is presented for a key building block, an active RC integrator with passive resistors. (FSA 3)--UCL, 2005

The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes. (FSA 3)--UCL, 2004