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Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

In this article, we propose a novel chaotic neuron circuit with memristive neural synapses, construct an architecture of memristive chaotic neural network (MCNN) and implement associative memory application of bipolar images. The proposed neuron circuit mainly consists of synapse module and neuron module with chaotic dynamics characteristics. The synapse module is composed of memristors which represent synaptic weights. The neuron module employs voltage feedback operational amplifiers to accomplish integral operation and output function. MCNN utilizes a memristor crossbar array to perform matrix operations and can process the information in parallel. In addition, the proposed circuit of MCNN can accomplish continuous recursive operations and meet different applications due to the programmability of the memristor. The ex-situ method is utilized to train the memristor crossbar array. Furthermore, the associative memory applications of bipolar images are carried out based on the constructed circuits of MCNN with three and nine neurons. The simulation results in PSPICE software testify the functions of the MCNN circuit.

The most important aspect of an artificial neuron circuit is energy consumption. An analog neuron circuit has a critical problem in that the energy consumption in the steady-state due to a short-circuit current in the first inverter is quite large. In this study, we first demonstrated an adaptive neuron circuit with a dual-gate positive feedback field-effect transistor (FBFET) and fabricated a neuron circuit by co-integrating the FBFET and a complementary metal-oxide semiconductor (CMOS) in a chip. The fabricated FBFET has an extremely low sub-threshold slope of less than 0.5 mV/dec and a low off current. The threshold voltage of the FBFET can be precisely controlled by the second gate bias. By adjusting the second gate bias, it is possible to implement spike-frequency adaptive characteristics in the neuron circuit. Moreover, the proposed neuron circuit with the FBFET can significantly reduce the power dissipation. In the neuron circuit, a short-circuit current is suppressed by adopting the FBFET in the first inverter. In a modified inverter with the FBFET, more than 50% total energy consumption was reduced by the FBFET. We implemented the modified inverter in which the FBFET is connected in parallel with an N-channel metal-oxide semiconductor. Moreover, we utilized the neural frequency adaptation characteristics in the neuron circuit by adjusting the threshold voltage of the FBFET. Finally, we analyzed the fabricated FBFET neuron circuit operation and power consumption compared to a conventional CMOS neuron circuit.

Spike-timing-dependent plasticity (STDP) is a fundamental synaptic learning rule observed in biology that leads to numerous behavioral and cognitive outcomes. Emulating STDP in electronic spiking neural networks with high-density memristive synapses is, therefore, of significant interest. While one popular method involves pulse-shaping the spiking neuron output voltages, an alternative approach is outlined in this article. The proposed STDP implementation uses time-varying dynamic resistance [ ${R}$ ( ${t}$ )] elements to achieve local synaptic learning from spike-pair STDP, spike triplet STDP, and firing rates. The ${R}$ ( ${t}$ ) elements are connected to each neuron circuit, thereby maintaining synaptic density and leveraging voltage division as a means of altering synaptic weight (memristor voltage). Example ${R}$ ( ${t}$ ) elements with their corresponding behaviors are demonstrated through simulation. A three-input-two-output network using single-memristor synaptic connections and ${R}$ ( ${t}$ ) elements is also simulated. Network-level effects, such as nonspecific synaptic plasticity, are discussed. Finally, spatiotemporal pattern recognition (STPR) using ${R}$ ( ${t}$ ) elements is demonstrated in simulation.

Purpose The purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model. Design/methodology/approach Numerical investigations for the tabu learning neuron model show the coexisting behaviors of bi-stability. To reproduce the numerical results by hardware experiments, a digitally FPGA-based neuron circuit is constructed by pure floating-point operations to guarantee high computational accuracy. Based on the common floating-point operators provided by Xilinx Vivado software, the specific functions used in the neuron model are designed in hardware description language programs. Thus, by using the fourth-order Runge-Kutta algorithm and loading the specific functions orderly, the tabu learning neuron model is implemented on the Xilinx FPGA board. Findings With the variation of the activation gradient, the initial-related coexisting attractors with bi-stability are found in the tabu learning neuron model, which are experimentally demonstrated by a digitally FPGA-based neuron circuit. Originality/value Without any piecewise linear approximations, a digitally FPGA-based neuron circuit is implemented using pure floating-point operations, from which the initial conditions-related coexisting behaviors are experimentally demonstrated in the tabu learning neuron model.

Voltages and currents in a memristor crossbar can be significantly affected due to nonideal effects such as parasitic source, line, and neuron resistance. These nonideal effects related to the parasitic resistance can cause the degradation of the neural network’s performance realized with the nonideal memristor crossbar. To avoid performance degradation due to the parasitic-resistance-related nonideal effects, adaptive training methods were proposed previously. However, the complicated training algorithm could add a heavy computational burden to the neural network hardware. Especially, the hardware and algorithmic burden can be more serious for edge intelligence applications such as Internet of Things (IoT) sensors. In this paper, a memristor-CMOS hybrid neuron circuit is proposed for compensating the parasitic-resistance-related nonideal effects during not the training phase but the inference one, where the complicated adaptive training is not needed. Moreover, unlike the previous linear correction method performed by the external hardware, the proposed correction circuit can be included in the memristor crossbar to minimize the power and hardware overheads for compensating the nonideal effects. The proposed correction circuit has been verified to be able to restore the degradation of source and output voltages in the nonideal crossbar. For the source voltage, the average percentage error of the uncompensated crossbar is as large as 36.7%. If the correction circuit is used, the percentage error in the source voltage can be reduced from 36.7% to 7.5%. For the output voltage, the average percentage error of the uncompensated crossbar is as large as 65.2%. The correction circuit can improve the percentage error in the output voltage from 65.2% to 8.6%. Almost the percentage error can be reduced to ~1/7 if the correction circuit is used. The nonideal memristor crossbar with the correction circuit has been tested for MNIST and CIFAR-10 datasets in this paper. For MNIST, the uncompensated and compensated crossbars indicate the recognition rate of 90.4% and 95.1%, respectively, compared to 95.5% of the ideal crossbar. For CIFAR-10, the nonideal crossbars without and with the nonideal-effect correction show the rate of 85.3% and 88.1%, respectively, compared to the ideal crossbar achieving the rate as large as 88.9%.

International audience; Aerospace applications are attractive candidates to embed Artificial Neural Networks despite their excellent parallel processing capability and reduced energy consumption. Nonetheless, the long-term exposure to incidence levels of ionizing radiation may degrade their physical components reducing, therefore, their reliability and expected lifetime. Thus, it is mandatory to face the challenge of enhancing the radiation hardening characteristics of a neural circuit before operating in harsh environments. A possible solution to substantially reduce long-term spurious effects caused by ionizing radiation (referred to as Total Ionizing Dose-TID) is to change the conventional rectangular MOS gate geometry to a non-standard topology referred to as Enclosed Layout Transistor (ELT). In the context of hardening a complete neuron circuit against TID effects, together with the well-established ELT paradigm, it is possible to exploit the inclusion of other hardened devices, for instance, the memory element. In this sense, the Oxide-based Resistive Random Access Memory (OxRAM) can be used as the memory element, which is inherently tolerant against ionizing radiation, and, hence, better suited for a fully hardened circuit. In this work, we propose to harden the design of an existing OxRAMbased neuron circuit [1] through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the n,pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180 nm technology, have been carried out to validate our proposed design. Additionally, we exploit two simulation setups. First, the OxRAM's behavior in a simple circuit configuration, to provide a better understanding of the OxRAM device. Second, the OxRAM-based neuron circuit, to evaluate the behavior of the proposed neuron circuit hardened with ELTs. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

Low-power neuromorphic hardware is indispensable for edge computing. In this study, we report the simulation results of a spiking neuron circuit. The circuit based on the Izhikevich neuron model is designed to reproduce various types of spikes and is optimized for low-voltage operation. Simulation results indicate that the proposed circuit successfully operates in the subthreshold region and can be utilized for reservoir computing.

Mathematical modifications have been made to the Izhikevich Neuron Model to allow for a simple, low-area digital hardware implementation with low computational intensity. The implemented neuron circuit only requires one input parameter to replicate all of the cortical neuron behaviours described by Izhikevich. The low hardware requirements of this neuron implementation make large, highly parallel digital spiking neural networks of this neuron feasible. Additionally, the model requires fewer external parameter changes to exhibit diverse neuron behaviours. The alterations made to create this novel model are presented in detail with a performance comparison to the original Izhikevich Neuron. Subsequently a digital hardware realization is presented and its performance is characterized.

Hybrid memristor-CMOS techniques have been recently proposed to build large-scale neural networks with learning capabilities. The intrinsic characteristics of memristors make them specially suited to implement synaptic connections between layers of spiking neurons, undergoing STDP learning (Spike-Timing-Dependent Plasticity) mechanisms when processing spikes with particular shapes. In a previous work, we proposed a tunable spiking neuron circuit which can generate spikes with controllable shape. In this work, the spike generator circuit has been implemented in FDSOI 28nm technology, and it has demonstrated its capability to produce spikes with pulse widths in the range between $8\mu {s}$ and 100ms.

International audience; Brain-inspired computing architectures, brought by Artificial Neural Networks (ANNs), are an attractive solution to reduce the energy consumption of the conventional von Neumann's computation, with an excellent parallel processing capability. Therefore, critical applications, such as Space & Satellite, which impose severe constraints in terms of power consumption and computing efficiency, are excellent candidates to embed such networks. Nonetheless, integrated circuits operating during long-term and cumulative exposure to incidence levels of ionizing radiation may have their physical components degraded, thus drastically reducing their reliability and expected lifetime. A possible solution to enhance the radiation hardening characteristics of a conventional bulk CMOS device is to use the non-standard gate geometry referred to as Enclosed Layout Transistor (ELT). In this work, we propose to harden the design of an existing OxRAM-based neuron circuit [1] through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the n,pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180 nm technology, have been carried out to validate our proposed design. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

To address the ever-increasing computational demands of machine learning applications, neuromorphic computing has emerged as a possible solution. The goal is to design a platform able to mimic the processing strategies of the brain. A neuromorphic system is composed by artificial neurons and synapses implemented in hardware with high level of integration. Such implementations entail challenges including power-efficiency, compactness and biophysical resemblance. This work proposes a new implementation of a neuron circuit, initially introduced by Wijekoon and Dudek. We show that the proposed neuron, designed in a standard 0.18µm CMOS process, consumes 58.5fJ/spike at 0.2V supply voltage. The area covered by the circuit is 16.8% of the area of the state-of-the-art implementation. This result was achieved by lowering the membrane capacitance and the number of transistors. In addition, spiking activity unfolds on a biological time scale - rather than accelerated. The circuit preserves the possibility of being adjusted by external biases to attain different firing patterns.

A perpendicular spin transfer torque (p-STT)-based neuron was developed for a spiking neural network (SNN). It demonstrated the integration behavior of a typical neuron in an SNN; in particular, the integration behavior corresponding to magnetic resistance change gradually increased with the input spike number. This behavior occurred when the spin electron directions between double Co2Fe6B2 free and pinned layers in the p-STT-based neuron were switched from parallel to antiparallel states. In addition, a neuron circuit for integrate-and-fire operation was proposed. Finally, pattern-recognition simulation was performed for a single-layer SNN.

In this paper, we proposed the current mirror based neuron circuit with the cascode structure added. Adding a cascode structure reduces the current fluctuation due to the membrane potential. And we compared two type of the neuron circuit in comparative operation, using inverters and a comparator. And we proposed the more efficient type of neuron circuit in terms of power consumption.

Neuromorphic circuits are becoming quite popular due to their ability to mimic the structure and behavior of human brain. Current research focuses on approximating spiking biological neuron behavior. Various neuron models have been proposed in the past that aid in investigating the behavior of neuronal systems mathematically. Mihalas–Niebur (MN) neuron model is one among them. In this paper log-domain based MN neuron model is implemented at 45 nm technology node. The paper studies the effects of process-temperature variations and also investigates the impact of Hot Carrier Injection (HCI), Bias Temperature Instability (BTI) on the performance of MN circuit. Average power consumption and spiking frequency are chosen as key performance measures to analyze the circuit performance before and after degradation.

Spiking neural networks (SNNs) are widely used in many fields because they work closer to biological neurons. However, due to its computational complexity, many SNNs implementations are limited to computer programs. First, this paper proposes a multi-synaptic circuit (MSC) based on memristor, which realizes the multi-synapse connection between neurons and the multi-delay transmission of pulse signals. The synapse circuit participates in the calculation of the network while transmitting the pulse signal, and completes the complex calculations on the software with hardware. Secondly, a new spiking neuron circuit based on the leaky integrate-and-fire (LIF) model is designed in this paper. The amplitude and width of the pulse emitted by the spiking neuron circuit can be adjusted as required. The combination of spiking neuron circuit and MSC forms the multi-synaptic spiking neuron (MSSN). The MSSN was simulated in PSPICE and the expected result was obtained, which verified the feasibility of the circuit. Finally, a small SNN was designed based on the mathematical model of MSSN. After the SNN is trained and optimized, it obtains a good accuracy in the classification of the IRIS-dataset, which verifies the practicability of the design in the network.

The pure circuit implementation of STDP is a worthwhile work. In this study, a novel spiking neuron circuit and STDP learning circuit based on memristors are designed. The proposed spiking neuron circuit, which is based on conventional leaky integrate-and-fire neuron and utilizes the nonlinear variation of memristance, is served to generate spikes. Different release thresholds and amplitudes of the spikes can be obtained through tuning circuit parameters. Extending on the spiking neuron circuit, a STDP learning circuit is built to perform unsupervised learning behaviors. Furthermore, a crossbar array architecture is finally considered to fabricate multi-input multi-output spiking neural network which also perform STDP learning effectively. Circuit simulation results in PSPICE prove the availability of the two proposed circuits.

Adaptive response to timely constant stimuli is a common feature of biological neurons. Implementation of neurons with such features is important for achieving biologically plausible networks using electronic systems. Emerging memristor devices open new horizons in electronically implementation of neural networks with high integration density and low power consumption. Promising potential applications can be considered for mem-elements (memristor, memcapacitor, and meminductor) with their built-in memory-properties. Since the dynamics of mem-elements makes them suitable for direct emulation of biological features of real neurons, it is expected that implementation of real neurons with complicated behavior to be straightforward using mem-element without complicating the implementation of the whole neuron circuit. Mem-elements are still unavailable commercially, so we utilize the mem-elements emulators to evaluate the feasibility of using these elements in the implementation of adaptive neurons. To ensure that there is the possibility of practical implementation of our neuron circuit, we used mem-elements emulators in SPICE simulations instead of mem-elements behavioral models. This work is among the first papers in the implementation of adaptive neurons using mem-elements. Here, using memristor and memcapacitor emulators the neuristor with adaptive behavior is implemented in SPICE environment. We use two different methods for induction of adaptive behavior to the neuristor response. In the first method, the capacitor in the primary circuit of neuristor is replaced with memcapacitor. Alternatively, the coupling resistor in the primary circuit of neuristor is replaced with the memristor in the second method. Results show that, the feature of memristor/memcapacitor in changing its resistance/capacitance during time upon excitation with current or voltage, makes the neuristor behavior to be adaptive in both methods, i.e. the neuristor shows the spike-frequency adaptation behavior in response to the continuous external stimulus, where the frequency of generated spikes depends on the duration of the external input stimulus.

The nonvolatility and resistance variability of memristor make it a candidate for emulating complex dynamic behaviors in the neural system. In this paper, the memristive neuron with homeostatic plasticity is implemented. The memristor is applied to the neuron circuit, and its memristance represents the membrane sensibility of neurons. Composed of a trigger module, a pulse generation module and a feedback module, the memristor-based neuron can adaptively adjust the firing rate of neuron and maintain it in the inherent firing rate range, which shows similarities to its biological counterpart. The proposed design can mimic firing rate behaviors of the electrophysiological experiment performed in rodent, where the homeostatic plasticity of neuron is inhibited by sleep signal and promoted by wake signal. Furthermore, all the simulations are conducted in Cadence PSPICE, and the functionality of the design is proved with the simulation.

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

We have developed a cellular neural network formed by simplified processing elements composed of thin-film transistors. First, we simplified the neuron circuit into a two-inverter two-switch circuit and the synapse device into only a transistor. Next, we composed the processing elements of thin-film transistors, which are promising for giant microelectronics applications, and formed a cellular neural network by the processing elements. Finally, we confirmed that the cellular neural network can learn multiple logics even in a small-scale neural network. Moreover, we verified that the cellular neural network can simultaneously recognize multiple simple alphabet letters. These results should serve as the theoretical bases to realize ultra-large scale integration for brain-type integrated circuits.

We present a low-power compact circuit for the event-driven readout of tactile sensors. The taxel is based on the POSFET device, a sensotronic unit where a piezo-electric material is deposited on the gate of a transistor, integrated with a Leaky-Integrate and Fire neuron circuit. This device encodes the applied force with trains of digital pulses, using the asynchronous Address Event Representation protocol. The instantaneous output spiking frequency is directly proportional to the force applied to the taxel. We show a full characterization of the device as well as quantitative measurements from a prototype fabricated on AMS CMOS 350-nm process. The taxel can reliably distinguish applied forces from 0.1 N up to 1.5 N.

The authors present a spike-triggered adaptive neuron circuit with input current modulation. Unlike adaptive neuron circuits where adaptation is realised by leakage modulation, the circuit presented in this Letter modulates the input current to membrane capacitor. Therefore, it is possible to reduce extra power consumption originating from increased leakage. Threshold voltage modulation of silicon on insulator (SOI) MOSFET by back gate effect is used to change the amount of injected current for the same input voltage. Through this method, the circuit in this work consumed 25.9% less power than the one modulating leakage.

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

Spiking neural networks (SNNs) are promising because they have the ability to represent signal strength information with a simple sequence of spikes having the same height. In this paper, we propose an RRAM-based analog neuron circuit for the weighted spiking neural network which is energy-efficient and hardware-friendly. We have designed the neuron circuit to show that the weighted spiking neural network can be implemented in analog and works properly.

Sensory information in the brain is encoded by intricate spiking patterns. Transient characteristics of individual action potentials may be used in neural encoding. Inspired by behaviors found in biological neurons, we have designed a neuromorphic circuit of a neuron that exhibits input-specific spiking. Our neuron circuit has multiple dendrites and uses properties of localized high-voltage-activated (HVA) Ca2+ channels to generate action potentials with distinct shapes depending on the location of stimulation received at input synapses. Through circuit simulations, we show that our neuron circuit can encode differences in spatial locations of input stimuli through precise characteristics of output spikes, and spike shapes are tunable. We then show that neuron circuits, in conjunction with astrocytes, can be used to replace damaged neurons processing sensory inputs with healthy neurons augmented to process their own sensory inputs as well as the inputs originally intended for the damaged neurons, using spiking shapes to signal input sources.

International audience; CMOS neuron circuits used to implement neuromorphic chips require extensive circuitry to program the memristive cell, thus eliminating most of the density advantage gained by the adoption of memristive synapses. This paper presents a CMOS neuron circuit that provides a compact and cost-efficient programming interface in which semiconductor capacitors are replaced by a memristive device. The neuron circuit also features an adjustable firing threshold with a strict control of the power consumption during the learning process.

Silicon neuron circuits emulate the electrophysiological behavior of real neurons and conductances. A detailed model mapped onto silicon neuron can be beneficial to the improvement of circuit design. Here we present a dynamic systems approach to obtain a detailed mathematical model describing the dynamics of a biophysically realistic silicon neuron. The approximate analytic solution of its firing rate fits simulation data from our neuron chip fabricated using a 130 nm CMOS process very well. Meanwhile, transistors that contribute critically to variation of firing activities are discovered, which helps the improvement of neuron mismatch.

The brained-inspired spiking neural networks (SNNs), which can be applied on visual information processing and speech recognition, is attracting great attention especially when combined with emerging electronic synapse (i.e. memristor). The neuron, transmitting and receiving spiking signals, is a vital component to realize the biological rules of SNNs, such as leaky-integrate-and-fire (LIF), inhibitory period, winner takes all (WTA) and bidirectional transmission. In this work, we propose and implement a novel spiking neuron circuit based on complementary- metal-oxide-semiconductor (CMOS) technology. Experimental results show that the neuron circuit can generate spiking pulses, realize lateral inhibition and change the weight of synapse.

International audience; Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.

Firing patterns discern the electrical activities in biological neurons when intracellular and extracellular ions are pumped into cells and exchanged there. Artificial neural circuits can be tamed to reproduce similar firing modes from biological neurons by applying appropriate physical stimuli. Photocurrent generated in the phototube can be used as a signal source, which can stimulate the neural circuits, while the involvement of which branch circuit will be much different because the channel current can control the dynamics of functional neuron to a different degree. In this paper, based on a nonlinear (FitzHugh-Nagumo, FHN) neural circuit composed of one capacitor, induction coil, nonlinear resistor, two ideal resistors and one periodical stimulus, the phototube is incorporated into different branch circuits for changing the channel current and the biophysical role of photocurrent is investigated. The dynamical equations of three types of system are unified, though they fall in different areas in parameter space. The membrane potential can be directly changed and firing modes are switched when photocurrent is activated to change the channel current by connecting the phototube to the capacitor. The induced current across the induction coil is regulated to balance the external stimulus when the phototube is connected to the induction coil in series. The two types of photosensitive neuron models constructed in this paper are compared with the photocurrent driven inductive branch showing that the photocurrent driven capacitive branch can very effectively regulate the membrane potential and greatly improve the photosensitive sensitivity.

In this paper, we propose two emulator circuits. Firstly, we present a novel memristor emulator based on operational transconductance amplifier (OTA) which is different from classical TiO2 memristor. This memristor emulator has a threshold switching mechanism. Secondly, we create a novel neuron circuit using proposed memristor, which is capable of generating spiking and bursting firing behaviors, with a biologically plausible spike shapes. The behavior of this neuron circuit can be adjusted by changing only one external biasing voltage. This neuron circuit mimics the behavior of cortical neurons, such as regular spiking (RS), intrinsic bursting (IB), chattering (CH) and fast spiking (FS). Proposed emulator circuits are compatible with VLSI systems and they can also be implemented by using discrete circuit components for different applications.

For more efficient computation, researches on neuromorphic systems suitable for neural networks have been conducted [1]. To replace conventional neuron circuits for integrate-and-fire (IF) function in neuromorphic systems, neuron devices with high density and low power consumption per spike have been studied [2, 3]. In the previous work, an n-type positive feedback (PF) device with steep switching characteristic was proposed for hardware-based neural networks [4]. In this paper, a p-type PF device with a charge storage layer is reported as neurons, which integrates signals using positive program bias (V PGM). Fig. 1 shows a top view of a p-type PF device and an energy band diagram of the PF operation. Doping concentration and length of n-/p-channels are 1×1018 cm-3 and 1 μm, respectively. Fin width (W) and height (H) of PF device is 35 nm and 100 nm, respectively. Thickness of gate dielectric (SiO2/Si3N4/SiO2) for the charge storage layer is 2/4.2/9 nm. As a gate bias (V G2) decreases, a hole-injection barrier decreases, and holes easily flow from anode to p-channel region. As more holes are injected to p-channel region, electron injection barrier decreases, and electrons easily flow from cathode to n-channel region. By positive feedback like this, an anode current (I A) abruptly flows from anode to cathode as shown in the Fig. 1 (c). As a V PGM pulse is applied to G1, a turn-on voltage (V on) is shifted slightly toward the positive voltage. After 15 V PGM pulses are applied, V on shifts from -0.3 V to 0.03 V as indicated by the diamond symbols in Fig. 1 (c). The change of V on by the number of pulses (V PGM) mimics the IF operation of neurons. Fig. 2 shows the symbol of the PF device and the repeated measurement for IF operation of the PF device as a parameter of V G1. IF and reset operations were measured by applying pulses of V G1 and V reset (-7 V) to G1. Reliable IF function with the repeated measurement is obtained in the PF device. As V G1 increases from 5.8 V to 6.2 V, the firing rate of the PF device increases due to the increase in electrons trapped in the charge storage layer (Si3N4). Fig. 3 (a) shows a conventional neuron circuit for the IF function in SNNs [5]. When the membrane voltage (V mem) exceeds the threshold of M2, M2 is turned on and the neuron is fired. However, even if the membrane voltage is less than the threshold voltage of M2, the subthreshold current continues to flow, resulting in a leakage path through M3 and M2, which takes up a large part of the standby power in neuron block. Hence, replacing M2 with a PF device with steep switching characteristics can effectively block this leakage path. Consequently, it can significantly reduce power consumption [4]. A 400–128–10 sized MLP network was simulated in the circuit level. A full network is composed of NOR flash synaptic array [6], current mirror, and IF block. The power consumed by each block is shown in Fig. 3 (b). MNIST data sets were presented over 8 time steps with each duration of 1 ms. IF block consumes 177.2 mW, which is about 28.3% of the total power consumption, and most of the power is consumed by the leakage or generation of output spikes. Networks that use only few spikes [7] have a higher rate of power consumption by the leakage than creating spikes. In addition, to accurately calculate the negative weight sum using the capacitor (C mem), it is necessary to set the initial membrane voltage to a positive value, which further increases power consumption by the leakage. By replacing M2 with a PF device, it is possible to construct a novel neuron by significantly reducing unnecessary power consumption in the conventional neurons. Reference [1] S. Yu, Proc. IEEE 106, 2 (2018) [2] J. Luo et al., IEDM Tech. Dig. 122 (2019) [3] S. Dutta et al., Sci. Rep. 7 (2017) [4] K. Choi et al., Front. Neurosci. 12, 704 (2018). [5] W. Kang et al., Int. Jt. Conf. Neural. Netw. 1 (2019). [6] C, Kim et al., IEEE Trans. Electron Devices 65, 5 (2018). [7] S. Kheradpisheh et al., Int. J. Neural. Syst. (2020). Figure 1

The homeostatic neuron circuit using a double-gate MOSFET is proposed to imitate a homeostasis functionality of a biological neuron in spiking neural networks (SNN) based on a spike-timing dependent plasticity (STDP). The threshold voltage (Vth) of the double-gate MOSFET is controlled by independent two-gate biases (VG1 and VG2). By using Vth change of the double-gate MOSFET in the neuron circuits, the fire rate of the output neuron is controlled. The homeostasis functionality is implemented by the operation of multi-neuron system based on the proposed neuron circuit. Through the SNN based on STDP using MNIST datasets, it is demonstrated that the recognition rate (~91%) of the SNN with the proposed homeostasis functionality is higher than that (~79%) of the SNN without the proposed homeostasis functionality. Also, the results of the recognition rate with the variations (σ/μ

In this paper, we proposed a neuron circuit, i.e., a two phase-change memory (2-PCM) neuron, to implement a backpropagation algorithm for hardware neural networks. PCM devices in the neuron are used for computing and storing signals. One of the PCM devices is used for storing the forward propagation signal, and the other is used for storing the backpropagation signal. This paper presents a new application of PCM devices in traditional artificial neural networks.

Neural networks have been used in a variety of fields including speech process, image recognition and video classification. In this work, based on 16/14nm FinFET technology, the feasibility of the neuron circuit using stochastic computing is evaluated. Considering the practical technology issues, the impact of random variabilities is carefully examined under ultra-low voltage. Using handwritten digital MNIST database, a reliable validation accuracy in neural network based on stochastic computing neuron circuits can be obtained with an ultra-low V dd . The design optimization procedure of neuron circuits is also proposed, which can decrease the energy consumption without the penalty of accuracy.

Adaptive firing rate of neuron plays an indispensable role in stabilizing the neural system, which means that the firing rate of neuron could be adjusted adaptively within an inherent range. In this paper, two aspects of implementing the adaptive firing rate are proposed at the circuit level. First, a memristor model is used in the neuron circuit to represent membrane sensitivity. Second, the threshold voltage of neuron circuit can be adjusted adaptively to change the firing rate. Combined these two methods, the adaptive firing rate of neuron circuit is realized effectively, which is in accordance with its biological counterpart. Furthermore, the proposed neuron circuit is applied in the spiking neural network to verify its functionality, where pattern recognition could be realized. All the simulations are carried out on PSPICE.

Current-mode active components provide linearity, wider bandwidth, and low power dissipation. Current conveyors which are a type of current mode active elements find large application area in circuit designs. In this paper, we present a novel neuron circuit based on a negative-type second-generation current conveyor (CCII‐). The circuit consists of only one CCII‐ and five MOS transistors and capable of generating fast-spiking firing behavior. Two transistors of them are used as capacitors in proposed neuron circuit. All simulation results are obtained as expected. The presented only-MOS based neuron circuit is compatible with VLSI systems.

A novel leaky integrate-and-fire (LIF) neuron circuit based on the gradual switching in resistive random access memory (RRAM) device is put forward, in which threshold modulation can be achieved. Its threshold modulation and spike generating functions are verified through HSPICE simulation. In unsupervised pattern recognition for handwritten digits in MNIST dataset, its advantage in improving the accuracy (from about 70% to more than 95%) is demonstrated. Benchmarking results indicate that this novel neuron is much faster and can save about 66% area compared to one previously proposed.

Etkili hesaplama işlemlerinde kullanılmak amacıyla insan beyin fonksiyonlarının ve genel prensiplerinin yapay nöronlar aracılığıyla nasıl taklit edileceğinin anlaşılması, mevcut bilim topluluğunu etkilemiştir. İşlevsellik, sinir hücreleri veya nöronlar olarak bilinen beyin hücrelerinin kendiliğinden birleşmesinden gelmektedir. İnsan beyin hücresinin moleküler düzeyde modellenmesi, biyolojik karmaşıklığı nedeniyle pratik değildir. Matematiksel yaklaşımlar ve teknolojik gelişmeler, yapay nöron modellerinin donanım ve yazılım uygulamasını kolaylaştırmaktadır. Sayısal yazılım araçları, yapay sinir ağlarında (YSA) biyolojik sinir ağı davranışını benimsemek için yapay sinirleri birbirine bağlamaktadır. YSA yazılım araçları, YSA'ların öğrenme becerileri, hesaplama gücü ve paralel işlem yoluyla yüksek hesaplama hızının olması nedeniyle sinir ağı uygulamalarının kullanımında geniş çapta kabul görmektedir. Ayrıca, YSA modelleri geleneksel hesaplama cihazlarından daha basittir. Yüksek performanslı sayısal işlem devrelerinde, bir nöron hücresi karmaşık problemlerin çözülebilme imkanlarını geliştirmektedir. Bu nedenle, temel bir nöron modeli, çip üzerinde bir YSA veya hibrit dijital devre oluşturma kapasitesine sahiptir. Bu çalışmada, biyolojik beyin hücresini taklit etmek için, çip üzerinde YSA oluşturma ve sızıntılı Topla ve Ateşle Nöron (Integrate and Fire Neuron, IFN) modelini sağlama potansiyeli olan bir Josephson Eklemi (Josephson Junction, JJ) tabanlı Yapay Nöron (Josephson Junction based Artificial Neuron, JJ-AN) devresi sunulmaktadır. Tasarlanan yapay nöron devresi, üç ana yapıdan oluşur: bir direnç tarafından kesintiye uğratılmış İki Eklemli Süperiletken Kuantum Girişim Aygıtı (Superconducting Quantum Interference Device, SQUID) yapısı (eşik döngüsü), seri direnç ve indüktans yapısı (sönümlenme döngüsü) ve eşik döngü ile sönümlenme döngü indüktansları arasındaki karşılıklı indüklenme. Sunulan model, sadece bir giriş ve bir çıkış portuna sahiptir ve bu yapı, devreyi nispeten basit olarak tanımlamaktadır. Bununla birlikte, nöron devresi, diğer nöron devreleriyle birlikte kullanılmasının yanı sıra Tek Akı Kuantum (Single Flux Quantum, SFQ) dijital kütüphane devreleriyle de bir araya getirildiği için böyle bir tasarımın optimizasyonu çok önemli bir süreçtir. Nöron modelinin çalışma frekansı 120 GHz'ye kadar gözlemlenmiştir. Araştırma için bir örnek olarak, farklı eşik değerleri oluşturan iki parametre seti, minimum çalışma aralığı sırasıyla %±23 ve %±7, eniyileyici tarafından ayarlanıp oluşturulmuştur., The current scientific community captivated by understanding the general principles of human brain functions, as a further matter, on how to mimic the abilities by utilizing artificial neurons for more efficient computing. Functionality comes from self-assembly of brain cells, known as nerve cells or neurons. Modeling human brain cell at a molecular level is not practical on account of its biological complexity. Mathematical approaches and technological developments led the hardware and software implementation of artificial neuron models easier. Computational software tools connect artificial neurons to each other to create Artificial Neural Network (ANN) to adopt biological neural network behavior. ANN software tools have gained extensive acceptance for wide range use of neural network applications because of learning abilities, computational power and speed through parallel processing. Furthermore, the models of ANN are simpler than conventional computing devices. For high performance computing circuits, a neuron cell can enhance the possibilities of solving complex problems. Therefore, a basic neuron model has the capacity of building an ANN on chip or hybrid digital circuits. vii To mimic the biological brain cell, this study shows a Josephson Junction (JJ) based Artificial Neuron (JJ-AN) circuit that satisfies the capability of creating ANN on chip and leaky Integrate and Fire Neuron (IFN) model. This artificial neuron circuit is formed by three main structures: a double-junction SQUID interfered with a resistor (threshold loop), adjoined resistor and inductance structure (decaying loop), and mutual conductance between threshold loop and decaying loop inductances. The proposed model has only one input and one output ports and it makes the circuit relatively simple. Nevertheless, optimization of such a design is a crucial process as neuron circuit is not only used together with other neuron circuits but also combined all together with Single Flux Quantum (SFQ) digital library circuits. Operation frequency of neuron model is observed up to 120 GHz. As an example for the research, two parameter sets that make different threshold values are converged by the modified optimizer that shows minimum margins of ±23% and ±7% respectively. The current scientific community captivated by understanding the general principles of human brain functions, as a further matter, on how to mimic the abilities by utilizing artificial neurons for more efficient computing. Functionality comes from self-assembly of brain cells, known as nerve cells or neurons. Modeling human brain cell at a molecular level is not practical on account of its biological complexity. Mathematical approaches and technological developments led the hardware and software implementation of artificial neuron models easier. Computational software tools connect artificial neurons to each other to create Artificial Neural Network (ANN) to adopt biological neural network behavior. ANN software tools have gained extensive acceptance for wide range use of neural network applications because of learning abilities, computational power and speed through parallel processing. Furthermore, the models of ANN are simpler than conventional computing devices. For high performance computing circuits, a neuron cell can enhance the possibilities of solving complex problems. Therefore, a basic neuron model has the capacity of building an ANN on chip or hybrid digital circuits. vii To mimic the biological brain cell, this study shows a Josephson Junction (JJ) based Artificial Neuron (JJ-AN) circuit that satisfies the capability of creating ANN on chip and leaky Integrate and Fire Neuron (IFN) model. This artificial neuron circuit is formed by three main structures: a double-junction SQUID interfered with a resistor (threshold loop), adjoined resistor and inductance structure (decaying loop), and mutual conductance between threshold loop and decaying loop inductances. The proposed model has only one input and one output ports and it makes the circuit relatively simple. Nevertheless, optimization of such a design is a crucial process as neuron circuit is not only used together with other neuron circuits but also combined all together with Single Flux Quantum (SFQ) digital library circuits. Operation frequency of neuron model is observed up to 120 GHz. As an example for the research, two parameter sets that make different threshold values are converged by the modified optimizer that shows minimum margins of ±23% and ±7% respectively. The current scientific community captivated by understanding the general principles of human brain functions, as a further matter, on how to mimic the abilities by utilizing artificial neurons for more efficient computing. Functionality comes from self-assembly of brain cells, known as nerve cells or neurons. Modeling human brain cell at a molecular level is not practical on account of its biological complexity. Mathematical approaches and technological developments led the hardware and software implementation of artificial neuron models easier. Computational software tools connect artificial neurons to each other to create Artificial Neural Network (ANN) to adopt biological neural network behavior. ANN software tools have gained extensive acceptance for wide range use of neural network applications because of learning abilities, computational power and speed through parallel processing. Furthermore, the models of ANN are simpler than conventional computing devices. For high performance computing circuits, a neuron cell can enhance the possibilities of solving complex problems. Therefore, a basic neuron model has the capacity of building an ANN on chip or hybrid digital circuits. vii To mimic the biological brain cell, this study shows a Josephson Junction (JJ) based Artificial Neuron (JJ-AN) circuit that satisfies the capability of creating ANN on chip and leaky Integrate and Fire Neuron (IFN) model. This artificial neuron circuit is formed by three main structures: a double-junction SQUID interfered with a resistor (threshold loop), adjoined resistor and inductance structure (decaying loop), and mutual conductance between threshold loop and decaying loop inductances. The proposed model has only one input and one output ports and it makes the circuit relatively simple. Nevertheless, optimization of such a design is a crucial process as neuron circuit is not only used together with other neuron circuits but also combined all together with Single Flux Quantum (SFQ) digital library circuits. Operation frequency of neuron model is observed up to 120 GHz. As an example for the research, two parameter sets that make different threshold values are converged by the modified optimizer that shows minimum margins of ±23% and ±7% respectively.

Nanoscale resistive memories are expected to fuel dense integration of electronic synapses for large-scale neuromorphic system. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in-situ learning and computing while driving a large number of resistive synapses is desired. This work presents a novel leaky integrate-and-fire neuron design which implements the dual-mode operation of current integration and synaptic drive, with a single opamp and enables in-situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18 $\mu$m CMOS technology. Measurements show neuron's ability to drive a thousand resistive synapses, and demonstrate an in-situ associative learning. The neuron circuit occupies a small area of 0.01 mm$^2$ and has an energy-efficiency of 9.3 pJ$/$spike$/$synapse.

We propose a simple and compact thyristor-based neuron circuit. The thyristor exhibits bi-stable characteristics that can mimic the action potential of the biological neuron, when it is switched between its OFF-state and ON-state with the help of assist circuit. In addition, a method of inter-neuron connection with synaptic devices is proposed, using double current mirror circuit. The circuit utilizes both short-term and long-term plasticity of the synaptic devices by flowing current through them and transferring it to the post-synaptic neuron. The double current mirror circuit is capable of shielding the pre-synaptic neuron from the post synapticneuron while transferring the signal through it, maintaining the synaptic conductance unaffected by the change in the input voltage of the post-synaptic neuron.

Recent neurophysiologic findings have shown that astrocytes (the most abundant type of glial cells) are active partners in neural information processing and regulate the synaptic transmission dynamically. Motivated by these findings, in the present research, an analog neuromorphic circuit to study neuron---astrocyte signaling is presented. In this analog circuit, the firing dynamics of the neuron is described by Izhikevich neuron circuit and the $$\hbox {Ca}^{2+}$$Ca2+ dynamics of a single astrocyte explained by a functional simplified model introduced by Montaseri et al. Using the proposed neuron---astrocyte circuit, it is demonstrated that the proposed analog astrocyte is able to activate the analog neuron or change the neuron spiking frequency through bidirectional communication. This suggests that analog astrocyte is capable of modulating spike transmission frequency. Moreover, our results suggest that the analog circuit of neuron---astrocyte crosstalk produces diverse neural responses and therefore enhances the information processing capabilities of the neuromorphic circuits. This is suitable for applications in reconfigurable neuromorphic devices which implement biologically brain circuits.

Spiking neural circuits have been designed in which the memristive synapses exhibit spike timing-dependent plasticity (STDP). STDP is a learning mechanism where synaptic weight (the strength of the connection between two neurons) depends on the timing of pre-and post-synaptic action potentials. A known capability of networks with STDP is detection of simultaneously recurring patterns within the population of afferent neurons. This work uses SPICE (simulation program with integrated circuit emphasis) to demonstrate the spatio-temporal pattern recognition (STPR) effect in networks with 25 afferent neurons. The neuron circuits are the leaky integrate-and-fire (I&F) type and implemented using extensively validated ambipolar nano-crystalline silicon (nc-Si) thin-film transistors (TFT) models. Ideal memristor synapses are driven by a nanoparticle memory thin-film transistor (np-TFT) with a short retention time attached to each neuron circuit output. This device serves to temporally modulate the conductance path from post-synaptic neurons, providing rate-based and timing-dependent learning. With this configuration, the use of a crossbar structures would also be possible, providing dense synaptic connections and potentially reduced energy consumption.

In this paper, a ring-oscillator (RO) based sub-1V leaky integrate-and-fire (I&F) neuron circuit is proposed, that can support user programmable refractory period and spike-frequency adaptation. Designed in CMOS 65-nm TSMC process, the neuron can operate from 0.9 V and has the unique feature that the same circuit can be programmed to operate either at biological time-scales or at accelerated time-scales. As ring-oscillators in nanometer CMOS are small compared to capacitors used in existing I&F silicon neuron (SiN), a large number of RO-based neurons can be integrated along with complex digital circuits to realize a single-chip Neuromorphic-SoC.

We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has shortterm and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.