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The power conversion efficiency (PCE) of metal halide perovskite solar cells (PSCs) has increased from 3.8 to 25.2% in the last decade, making perovskite the most promising material for future solar cells. However, further PCE and stability improvement are important for successful commercialization. Therefore, the aim of this thesis is to investigate ways of increasing PCE and addressing instability of PSCs. Initial PCE increase has been observed during ambient storage for many PSCs. Through a series of experiments, the origin of the storage effect was attributed to a combination of i) defect reduction in perovskite, ii) conductivity increase, and iii) evolution of the highest occupied molecular orbital (HOMO) in spiro-OMeTAD. In particular, the HOMO level change was revealed to play a significant role in PCE improvement. In terms of strategy for improving PCE, a novel passivation technique was developed by forming 2D/3D perovskite thin layer using a mixture of formamidinium iodide and iso-butylammonium iodide on the perovskite layer. This technique achieved a maximum PCE of 21.7%, while simultaneously enhancing device light and moisture stability. The defect density reduction, the uniform surface coverage of the passivation material and the suppressed ion migration by bulky organic cation were found to be the key parameters for PCE and stability improvement. Storage effect was also studied for these passivated PSCs. It is found that the changed conduction band of passivated perovskite influenced the initial temporal change of PCE, suggesting the importance of interface band alignment by passivation and conductive materials. Also, despite significantly suppressed non-ideal recombination at the surface/interface by passivation, analysis of the dominant recombination revealed the need for defect reduction in bulk perovskite. Consequently, by engineering the composition of bulk perovskite layers to decrease defects, PCE of 22.2% was achieved. Finally, the effects of removing one of hole transport material (HTM) additives, 4-tert-butylpyridine (tBP) (via HTM solvent engineering) on device performance and thermal stability were investigated. The suppressed morphological change at high temperature for tBP-free HTM was the reason for thermal stability improvement. This work shows that comparable efficiencies can still be achieved without the use of the thermally unstable HTM dopant.

Hierarchical Temporal Memory is a brain inspired memory prediction framework modeled after the uniform structure and connectivity of pyramidal neurons found in the human neocortex. Similar to the neocortex, Hierarchical Temporal Memory processes spatiotemporal information for anomaly detection and prediction. A critical component in the Hierarchical Temporal Memory algorithm is the Spatial Pooler, which is responsible for processing feedforward data into sparse distributed representations. This study addresses three fundamental research questions for Hierarchical Temporal Memory algorithms. What are the metrics for understanding the semantic content of sparse distributed representations? The semantic content and relationships between representations was visualized with uniqueness matrices and dimensionality reduction techniques. How can spatial semantic information in images be encoded into binary representations for the Hierarchical Temporal Memory's Spatial Pooler? A Contractive Autoencoder was exploited to create binary representations containing spatial information from image data. The uniqueness matrix shows that the Contractive Autoencoder encodes spatial information with strong spatial semantic relationships. The final question is how can vector operations of sparse distributed representations be enhanced to produce separable representations? A binding operation that results in a novel vector was implemented as a circular bit shift between two binary vectors. Binding of labeled sparse distributed representations was shown to create separable representations, but more robust representations are limited by vector density.

Transactional memory (TM) has emerged as a promising synchronization abstraction for multi-core architectures. Unlike traditional lock-based approaches, TM shifts the burden of implementing threads synchronization from the programmer to an underlying framework using hardware (HTM) and/or software (STM) components. Although TM can be leveraged to implement transactional data structures (i.e., those where multiple operations are allowed to execute atomically, all-or-nothing, according to the transaction paradigm), its intensive speculation may result in significantly lower performance than the optimized concurrent data structures. This poor performance motivates the need to find other, more effective, alternatives for designing transactional data structures without losing the simple programming abstraction proposed by TM. To do so, we identified three major challenges that need to be addressed to design efficient transactional data structures. The first challenge is composability, namely allowing an atomic execution of two or more data structure operations in the same way as TM provides, but without its high overheads. The second challenge is integration, which enables the execution of data structure operations within generic transactions that may contain other memory- based operations. The last challenge is modeling, which encompasses the necessity of defining a unified formal methodology to reason about the correctness of transactional data structures. In this dissertation, we propose different approaches to address the above challenges. First, we address the composability challenge by introducing an optimistic methodology to effi- ciently convert concurrent data structures into transactional ones. Second, we address the integration challenge by injecting the semantic operations of those transactional data struc- ture into TM frameworks, and by presenting two novel STM algorithms in order to enhance the overall performance of those frameworks. Finally, we address the modeling challenge by presenting two models for concurrent and transactional data structures designs. • Our first main contribution in this dissertation is Optimistic transactional boosting (OTB), a methodology to design transactional versions of the highly concurrent optimistic (i.e., lazy) data structures. An earlier (pessimistic) boosting proposal added a layer of abstract locks on top of existing concurrent data structures. Instead, we propose an optimistic boosting methodology, which allows greater data structure-specific optimizations, easier integration with TM frameworks, and lower restrictions on the operations than the original (more pessimistic) boosting methodology. Based on the proposed OTB methodology, we implement the transactional version of two list-based data structures (i.e., set and priority queue). Then, we present TxCF-Tree, a balanced tree whose design is optimized to support transactional accesses. The core optimizations of TxCF-Tree's operations are: providing a traversal phase that does not use any lock and/or speculation and deferring the lock acquisition or physical modification to the transaction's commit phase; isolating the structural operations (such as re-balancing) in an interference-less housekeeping thread; and minimizing the interference between structural operations and the critical path of semantic operations (i.e., additions and removals on the tree). • Our second main contribution is to integrate OTB with both STM and HTM algorithms. For STM, we extend the design of both DEUCE, a Java STM framework, and RSTM, a C++ STM framework, to support the integration with OTB. Using our extension, programmers can include both OTB data structure operations and traditional memory reads/writes in the same transaction. Results show that OTB performance is closer to the optimal lazy (non-transactional) data structures than the original boosting algorithm. On the HTM side, we introduce a methodology to inject semantic operations into the well-known hybrid transactional memory algorithms (e.g., HTM-GL, HyNOrec, and NOre- cRH). In addition, we enhance the proposed semantically-enabled HTM algorithms with a lightweight adaptation mechanism that allows bypassing the HTM paths if the overhead of the semantic operations causes repeated HTM aborts. Experiments on micro- and macro- benchmarks confirm that our proposals outperform the other TM solutions in almost all the tested workloads. • Our third main contribution is to enhance the performance of TM frameworks in gen- eral by introducing two novel STM algorithms. Remote Transaction Commit (RTC) is a mechanism for executing commit phases of STM transactions in dedicated server cores. RTC shows significant improvements compared to its corresponding validation based STM algorithm (up to 4x better) as it decreases the overhead of spin locking during commit, in terms of cache misses, blocking of lock holders, and CAS operations. Remote Inval- idation (RInval) applies the same idea of RTC on invalidation based STM algorithms. Furthermore, it allows more concurrency by executing commit and invalidation routines concurrently in different servers. RInval performs up to 10x better than its corresponding invalidation based STM algorithm (InvalSTM), and up to 2x better than its corresponding validation-based algorithm (NOrec). • Our fourth and final main contribution is to provide a theoretical model for concurrent and transactional data structures. We exploit the similarities of the OTB-based data structures and provide a unified model to reason about the correctness of those designs. Specifically, we extend a recent approach that models data structures with concurrent readers and a single writer (called SWMR), and we propose two novel models that additionally allow multiple writers and transactional execution. Those models are more practical because they cover a wider set of data structures than the original SWMR model.

Self-learning hardware systems, with high-degree of plasticity, are critical in performing spatio-temporal tasks in next-generation computing systems. To this end, hierarchical temporal memory (HTM) offers time-based online-learning algorithms that store and recall temporal and spatial patterns. In this work, a reconfigurable and scalable HTM architecture is designed with unique pooling realizations. Virtual synapse design is proposed to address the dynamic interconnections occurring in the learning process. The architecture is interweaved with parallel cells and columns that enable high processing speed for the cortical learning algorithm. HTM has two core operations, spatial and temporal pooling. These operations are verified for two different datasets: MNIST and European number plate font. The spatial pooling operation is independently verified for classification with and without the presence of noise. The temporal pooling is verified for simple prediction. The spatial pooler architecture is ported onto an Altera cyclone II fabric and the entire architecture is synthesized for Xilinx Virtex IV. The results show that 91% classification accuracy is achieved with MNIST database and 90% accuracy for the European number plate font numbers with the presence of Gaussian and Salt & Pepper noise. For the prediction, first and second order predictions are observed for a 5-number long sequence generated from European number plate font and ~95% accuracy is obtained. Moreover, the proposed hardware architecture offers 3902X speedup over the software realization. These results indicate that the proposed architecture can serve as a core to build the HTM in hardware and eventually as a standalone self-learning hardware system.

There is a significant interest in the research community to develop large scale, high performance implementations of neuromorphic models. These have the potential to provide significantly stronger information processing capabilities than current computing algorithms. This thesis examines the parallelization of two recent biologically inspired hierarchical Bayesian cortical models onto recent multicore architectures. These models have been developed recently based on new insights from neuroscience and have several advantages over traditional neural networks. In particular, they need far fewer network nodes to simulate a large scale cortical model than traditional neural networks, making them computationally more efficient. This is the first study of the parallelization of this class of models onto multicore processors. Results indicate that the models can take advantage of parallelism present in the processors to provide significant speedups on multicore architectures. These models are further shown to scale well on a cluster of 336 PS3s available at the Air Force Research Lab which is shown to emulate between 10E8 to 1010 neurons. In particular, the results indicate that a cluster of Playstation 3s can provide an economical, yet powerful, platform for simulating large scale neuromorphic models.