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Context. The growing prevalence and potential impact of cloud computing technology have sparked significant attention amongst IT industry and academia. It offers potential clients a wide range of services which are universally accessible, acquirable, releasable, and payable on the fly based on the amount of usage. Many IT-based organisations are moving their legacy software applications to cloud environments. An effective method for conducting such transition is crucial to a successful migration. The literature review reveals that the methodological aspect of the cloud migration has not been well addressed, despite calls expressed by several researchers to resolve this issue. The existing knowledge about cloud migration process is fragmented over the literature, narrow in tactical focus with heterogeneous viewpoints, and lacking support for creating customised methods, that fit given cloud migration scenarios. Objective. By adopting the design science paradigm, this research proposes a framework, which provides a generic process model of cloud migration with associated guidelines. The model can be reused and tailored for creating, configuring, and maintaining situational methods for various cloud migration scenarios. Method. The proposed framework is based a model-driven software development approach and offers two functionalities: (i) an overarching and platform-independent process model which captures domain constructs relevant to the cloud migration which a typical cloud migration may entail; and (ii) a tailoring procedure which aids creating, fine-tuning, standardising, and sharing situational methods for given cloud migration scenarios through reusing the process model. The framework is iteratively evaluated and refined by feedback received from domain experts and case studies. Contributions. The framework facilitates consistent communication and efficient knowledge sharing and exchange in the cloud migration domain. It also underpins a substrate for creating, standardising, maintaining, and publishing situational methods for various cloud migration scenarios.

Many businesses which use mainframe systems are unreliable these days and are facing the problem of data inconsistency and inaccuracy. Moreover the costs incurred in maintaining these systems keeps on increasing. As the competitors are migrating over to the new technologies and tools available in the market, it is necessary for these businesses to migrate to new environment which is efficient, consistent and reliable to stay in the market and the technologies used in the current environment have become obsolete or no longer serve the business purpose. This report summarizes the various methodologies, procedures and techniques involved in successfully migrating the data to modern systems. The practical work carried out for the capstone project is the development/building of application for data migration that is tailor-made for the client and their specific needs. In the process of data migration, we profile the existing data which helps in determining the structure and completeness of the data, in turn results in improved data quality. This report also contains data analysis that are carried on basis of profiled data and transforming the data accordingly to meet the new business needs. Agile software development life cycle is followed in the application building process as it uses iterative and incremental approach, bridging the gap between business owners and application developers as the end users are involved in each iterative phase. This report concludes with results that are obtained from successful data migration from the perspective of business needs and recommendations that could be implemented in the process of scaling of application

Increasing the number of processors has become the mainstream for the modern chip design approaches. However, most applications are designed or written for single core processors; so they do not benefit from the numerous underlying computation resources. Moreover, there exists a large base of legacy software which requires an immense effort and cost of rewriting and re-engineering to be made parallel. In the past decades, there has been a growing interest in automatic parallelization. This is to relieve programmers from the painful and error-prone manual parallelization process, and to cope with new architecture trend of multi-core and many-core CPUs. Automatic parallelization techniques vary in properties such as: the level of paraellism (e.g., instructions, loops, traces, tasks); the need for custom hardware support; using optimistic execution or relying on conservative decisions; online, offline or both; and the level of source code exposure. Transactional Memory (TM) has emerged as a powerful concurrency control abstraction. TM simplifies parallel programming to the level of coarse-grained locking while achieving fine-grained locking performance. This dissertation exploits TM as an optimistic execution approach for transforming a sequential application into parallel. The design and the implementation of two frameworks that support automatic parallelization: Lerna and HydraVM, are proposed, along with a number of algorithmic optimizations to make the parallelization effective. HydraVM is a virtual machine that automatically extracts parallelism from legacy sequential code (at the bytecode level) through a set of techniques including code profiling, data dependency analysis, and execution analysis. HydraVM is built by extending the Jikes RVM and modifying its baseline compiler. Correctness of the program is preserved through exploiting Software Transactional Memory (STM) to manage concurrent and out-of-order memory accesses. Our experiments show that HydraVM achieves speedup between 2×-5× on a set of benchmark applications. Lerna is a compiler framework that automatically and transparently detects and extracts parallelism from sequential code through a set of techniques including code profiling, instrumentation, and adaptive execution. Lerna is cross-platform and independent of the programming language. The parallel execution exploits memory transactions to manage concurrent and out-of-order memory accesses. This scheme makes Lerna very effective for sequential applications with data sharing. This thesis introduces the general conditions for embedding any transactional memory algorithm into Lerna. In addition, the ordered version of four state-of-art algorithms have been integrated and evaluated using multiple benchmarks including RSTM micro benchmarks, STAMP and PARSEC. Lerna showed great results with average 2.7× (and up to 18×) speedup over the original (sequential) code. While prior research shows that transactions must commit in order to preserve program semantics, placing the ordering enforces scalability constraints at large number of cores. In this dissertation, we eliminates the need for commit transactions sequentially without affecting program consistency. This is achieved by building a cooperation mechanism in which transactions can forward some changes safely. This approach eliminates some of the false conflicts and increases the concurrency level of the parallel application. This thesis proposes a set of commit order algorithms that follow the aforementioned approach. Interestingly, using the proposed commit-order algorithms the peak gain over the sequential non-instrumented execution in RSTM micro benchmarks is 10× and 16.5× in STAMP. Another main contribution is to enhance the concurrency and the performance of TM in general, and its usage for parallelization in particular, by extending TM primitives. The extended TM primitives extracts the embedded low level application semantics without affecting TM abstraction. Furthermore, as the proposed extensions capture common code patterns, it is possible to be handled automatically through the compilation process. In this work, that was done through modifying the GCC compiler to support our TM extensions. Results showed speedups of up to 4× on different applications including micro benchmarks and STAMP. Our final contribution is supporting the commit-order through Hardware Transactional Memory (HTM). HTM contention manager cannot be modified because it is implemented inside the hardware. Given such constraint, we exploit HTM to reduce the transactional execution overhead by proposing two novel commit order algorithms, and a hybrid reduced hardware algorithm. The use of HTM improves the performance by up to 20% speedup.

With the widespread use of the Internet and its associated technologies, enterprises have to evolve in the way they are conducting business. 'e-business applications' refer to a new class of distributed applications that involves the Internet as a communication platform. Each e-business application supports the full automation of business processes that can span across multiple enterprises. For a given application domain that involves e-business application development, a number of design decisions that best fulfil stakeholders requirements have to be made. One important issue is the reuse of functionality which exists within legacy systems that can belong to one or more enterprises within the same domain. Most existing design approaches are inadequate in supporting the exploration of all design combinations. Moreover, there is little work on how to identify the best design decisions systematically for a given application domain. In this thesis we present a pattern-based approach that addresses the architectural design of e-business applications. We identify a number of architectural patterns whose instantiation on a given design problem correspond to different architectural design alternatives. We also identify models that enable the estimation of quality attributes for such alternatives. Then we investigate and utilise methods to select the best pattern for a given design problem. We also describe the process of generating the alternative architectures, estimating their qualities, and then ranking them with respect to any quality attribute or a combination of quality attributes. We validate this approach on a real life case study in the area of capital markets. The case study concerns realistic e-business applications that rely on existing legacy applications. The validation exercise has produced predictions which have been compared with actual design decisions that have been made. The thesis also proposes a framework for the systematic identification of architectural patterns. An additional set of architectural patterns and their impact on the case study are discussed. The main contribution of this thesis is in the identification of patterns and quality attributes models for the architectural design of e-business applications that aid in the systematic selection of the most appropriate architectural pattern for a given problem context.

A digital board typically contains a heterogeneous mixture of chips: microprocessors, memory, control and I/O logic. Different testing techniques are needed for each of these components. To test the whole board, these techniques must be integrated into an overall testing strategy for the board. In this thesis, we have applied a behavioral testing scheme to test the board. Each component chip is tested by observing the behavior of the system in response to the test code, i.e. the component under test is not isolated from the rest of the circuit during test. This obviates the need for the extra hardware used for isolating the chips that is required for structural testing. But this is done at the cost of reduced fault location, although fault detection is still adequate. We have applied the start small approach to behavioral testing. We start by testing a small core of functions. Then, only those functions already tested are used to test the remaining behavior. The grand goal is testing the whole board. This is divided into goals for testing each of the individual chips, which is further subdivided into sub-goals for each of the sub-functions of the board or sub-goals for testing for the most common faults in a component. Each component is tested one by one. Once a component passes, it is put in a passed items set and then can be used in testing the remaining components. Using the start small approach helps isolate the faults to the chip level and thus results in better fault location than the simple behavioral testing scheme in which there is no concept of passed items set and its usage. As an example, this testing approach is applied to a microcontroller based temperature sensor board. This code is run on the VHDL model of the system, and then also on the actual system. For modeling the system in VHDL, Synopsys Smart model library components are used. Faults are injected in the system and then the performance of the strategy is evaluated. This strategy is found to be very effective in detecting internal faults of the chip and locating the faults to the chip level. The interconnection faults are difficult to locate although they are detected in most of the cases. Different scenarios for incorporating this scheme in legacy systems are also discussed.