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Digital electronic industry today relies on Nyquist sampling theorem, which requires to double the size (sampling rate) of the signal representation on the Fourier basis to avoid information loss. However, most natural signals have very sparse representations on some other orthogonal (non-Fourier) basis. This mismatch implies a large redundancy in Nyquist-sampled data, making compression a necessity prior to storage or transmission. Recent advances in compressive sensing (CS) theory offer us an alternative data acquisition framework, which can greatly impact power-starved applications such as wireless sensors. CS techniques provide a universal approach to sample compressible signals at a rate significantly below the Nyquist rate with limited information loss. Therefore, CS is a promising technology for realizing configurable, cost-effective, miniaturized, and ultra-low-power data acquisition devices for mobile and wearable applications.However, the digital signal processing of compressively-sampled data involves solving a sparse approximation problem, which requires iterative-searching algorithms that have high computational complexity and require intensive memory access. As a result, existing software solutions are neither energy-efficient nor cost-effective for real-time processing of compressively-sampled data, especially when the processing is to be performed on energy-limited devices. To solve this problem, this dissertation presents a scalable VLSI architecture that can be implemented on field-programmable gate arrays (FPGAs) or system-on-chips (SoCs) to perform dedicated-hardware-driven sparse approximation. A VLSI soft-IP core of the sparse approximation engine is developed in Verilog-HDL, which supports a floating-point data format with 10 design parameters, providing a high dynamic range and the flexibility for application-specific user customizations. Taking advantage of the algorithm-architecture co-design that leverages algorithm reformulations, configurable architectures, and efficient memory mapping schemes, the proposed VLSI architecture features a 100% utilization of the computing resources and is scalable in terms of computation parallelism and memory capability.The hardware emulation of the soft-IP core on a 28-nm Xilinx Kintex-7 FPGA shows that our design achieves the same level of accuracy as the double-precision C program running on an Intel Core i7-4700MQ mobile processor, while providing 47-147x speed-up for ECG signal reconstruction. Furthermore, a 12-237 KS/s 12.8 mW sparse approximation engine chip is realized in a 40-nm CMOS technology for enabling the mobile data aggregation of compressively sampled biomedical signals in CS-based wireless health monitoring systems. The measurement results show that the sparse approximation engine chip operating at the minimum energy point achieves a real-time throughput for reconstructing 61-237 channels of biomedical signals simultaneously with

In this thesis, an FPGA implementation of a factorization processor for algebraic soft-decision Reed-Solomon (RS) decoding is first presented. The design is based on the root-order prediction architecture and extensible for the factorization of polynomials with designated degrees. Parallel processing is exploited to speed up the polynomial updating involved in the factorization. To resolve the data dependency issue in parallel polynomial updating, an efficient coefficient storage and transfer scheme with small memory requirement and low latency is proposed. Synthesis results show that the factorization processor for a (255, 239) RS code with maximum multiplicity four can achieve an average decoding speed of 226 Mbps on a Xilinx Virtex-II FPGA device when the frame error rate is less than 10-2.Next, an FPGA implementation of a factorization processor for algebraic soft-decision bit-level generalized minimum distance (BGMD) RS decoding is presented. The BGMD factorization processor utilizes a low-latency and prediction-free scheme for root computation. Furthermore, parallel processing architectures and efficient coefficient storage schemes are employed to reduce the latency. Synthesis results show that the BGMD factorization processor for a (255, 239) RS code with maximum multiplicity two can achieve a decoding speed of 815 Mbps on a Xilinx Virtex-II FPGA device.Prior research efforts have been focusing on using BCH codes for error correction in multi-level cell (MLC) NAND flash memory. However, BCH codes often require highly parallel implementations to meet the throughput requirement. As a result, large area is needed. In this thesis, RS codes are proposed to be used for the error correction inMLC flash memory. A (828, 820) RS code has almost the same rate and length in terms of bits as a BCH (8248, 8192) code. Moreover, it has at least the same error-correcting performance in flash memory applications. Nevertheless, with 70% of the area, the RS decoder can achieve a throughput that is 121% higher than the BCH decoder. A novel bit mapping scheme using Gray code is also proposed. Compared to direct bit mapping, the proposed scheme can achieve 0.02 dB and 0.2dB additional gains by using RS and BCH codes, respectively, without any overhead.

The DNA sequence databases have been doubling in size every 18 months or so. This has forced the development of software and hardware systems for managing and searching these collections. An interesting problem in Genomic research is the identification of significant patterns of bases that provide control signals to the cellular protein-production machinery, a symbolic pattern recognition task for which computers are particularly well suited. The immense volume of data requires a large amount of time and computational effort to perform a simple database search. Given a string 'P' (|P|= m) called the pattern and a longer string 'T' (|T|=n) called the text, the exact matching problem is to find all occurrences, if any, of pattern 'P' in text 'T'. Many software algorithms have been developed to reduce the complexity from Θ(mn) to Θ(m+n). In this thesis, a special purpose hardware based system is described for finding clusters of patterns (max|P| = 30),in a DNA sequence, defined over a specific alphabet. By doing a number(d) of parallel computations, the complexity is further reduced to Θ(n/d). The architecture is scalable and is designed to be implemented on Virtex FPGAs. This design is extremely useful in the identification of binding sites of transcription factors.