1. Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications
- Author
-
Jur, Jesse Stephen
- Subjects
- dc magnetron sputtering, physical vapor deposition, tungsten oxide, tungsten, W, tantalum nitride, TaN, lanthanum, lanthanum oxide, La, La2O3, La2SiO5, lanthanum silicate, La2Si2O7, Ho, holmium, holmium oxide, cation diffusion, back-side SIMS, secondary ion mass spectroscopy, SIMS, XRD, x-ray diffraction, molecular beam deposition, PMA, XPS, x-ray photoemission spectroscopy, post metallization anneal, RCA, chemical oxide, metal oxide semiconductor field effect transistor, MBE, silica, SiO2, interfacial layer, gate dielectric, dielectric, silicate, oxide, high-kappa, EOT, equivalent oxide thickness, high-k, band diagram, valance band offset, conduction band offset, band gap energy, effective work function, work function, voltage shift, threshold voltage, flat band voltage, leakage current, capacitance, mobility, electronic materials, scaling, Moore?s Law, MIS, MOS, MOSFET, high resolution transmission electron microscopy, HRTEM, RTA, rapid thermal anneal, PVD, tantalum, Ta, gate electrode, metal electrode, hafnium silicate, hafnium oxide, hafnium, ytterbium, ytterbium oxide, Yb, dysprosium oxide, dysprosium, Dy, E-beam evaporation, thermal evaporation, forming gas anneal, ozone, ammonia anneal, FGA
- Abstract
The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high leakage current between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high- dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-K dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. It is shown that optimization of low-temperature processing can result in MOS devices with an equivalent oxide thickness (EOT) as low 5 Å and a leakage current density of 5.0 A⁄cm2. High-temperature processing, consistent with a MOSFET source-drain activation anneal, yields MOS devices with an EOT as low as 1.1 nm after optimization of the TaN/W electrode properties. The decrease in the device effective work function (phi_M,eff) observed in these samples is examined in detail. First, as a La2O3 capping layer on HfSiO(N), the shift yields ideal-phi_M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of phi_M,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.
- Published
- 2007