22 results on '"Beyne, Eric"'
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2. Impact of gate-level clustering on automated system partitioning of 3D-ICs
3. Simulation of Cu pad expansion in wafer-to-wafer Cu/SiCN hybrid bonding
4. Vapor deposited thin organic–inorganic capping layers preventing copper line oxidation in polymer-based RDL technologies
5. Effects of isothermal storage on grain structure of Cu/Sn/Cu microbump interconnects for 3D stacking
6. Etch process modules development and integration in 3D-SOC applications
7. Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly
8. RIE dynamics for extreme wafer thinning applications
9. Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects
10. Influence of Si wafer thinning processes on (sub)surface defects
11. Edge trimming for surface activated dielectric bonded wafers
12. Dielectric liner reliability in via-middle through silicon vias with 3 Micron diameter
13. Formation, processing and characterization of Co–Sn intermetallic compounds for potential integration in 3D interconnects
14. Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling
15. Degradation of Cu6Sn5 intermetallic compound by pore formation in solid–liquid interdiffusion Cu/Sn microbump interconnects
16. On the thermal stability of physically-vapor-deposited diffusion barriers in 3D Through-Silicon Vias during IC processing
17. Multilayer thin-film technology enabling technology for solving high-density interconnect and assembly problems
18. Direct gold and copper wires bonding on copper
19. The influence of packaging materials on RF performance
20. Modified micro–macro thermo-mechanical modelling of ceramic ball grid array packages
21. Parametric compact models for the 72-pins polymer stud grid array™
22. Interconnect technologies for multi-chip modules: high frequency characterization and loss analysis
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