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Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 degC a surface roughness below 1 nm can be achieved together with enhancement carrier mobility. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

In this study, Ge1-x-y-zSnxSiyCz layers (0.01[?]x[?] 0.06, 0[?]y[?]0.02 and 0[?]z[?]0.01) have been successfully grown at 280-330 C/aC on Ge and Si by using RPCVD technique. It was demonstrated that the quality of epitaxial layers is dependent on the growth parameters, layer thickness and the quality of Ge virtual layer. It was found that a proper strain balance in the matrix during the epitaxy where the Si is adjusted carefully with the Sn flux improves the incorporation of Sn in Ge matrix. A similar improvement of Sn incorporation has been observed for phosphorous, boron and carbon doping in GeSn layers as well. This is explained by the compensation of the compressive strain caused by Sn by the tensile strain induced by Si to obtain the minimum energy in Ge matrix. This behavior was not observed for relaxed GeSn layers and Sn incorporation could be controlled only by the growth parameters. The thermal stability of GeSn is an important integration issue for device fabrication. The thermal stability of P- and B-doped GeSn layers was studied by rapid thermal annealing (RTA) in range of 400-600 C/aC and compared with intrinsic layers. The GeSn layers were stable up to 550 C/aC while the P-doped layers showed strain relaxation readily at 450 C/aC. The epitaxial quality of epi-layers was evaluated in terms of oxygen and water vapor contamination. The level of oxygen during epitaxy was as low as 10 ppb and the contamination amount was found as low as 1017 cm-3.

In this study, a novel method using Focus Ion Beam (FIB) technique was applied to scale down Si1-xGex wires (x=0.27-0.57) to 20 nm width. Originally, the wires were processed by using I-line lithography and dry etching of SiGe on oxide (SGOI) substrates. The SGOI wafers were processed through condensation method where a SiGe/Si layer was grown in the beginning on SOI wafers and oxidized at 850-1050 degC. The shape of the nanowires (NWs) during the successive FIB cutting was examined by scanning electron microscopy (SEM) and the carrier transport through the NWs was checked by resistivity measurements. The contact resistance was reduced by Ni-silicide prior to metallization. The fabricated NWs were also suspended by tilting FIB. The results present the limitations and challenges of FIB technique to create NWs for advanced sensors and transistors.

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with enhancement carrier mobility. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

In this study, Ge1-x-y-zSnxSiyCzlayers (0.01≤x≤ 0.06, 0≤y≤0.02 and 0≤z≤0.01) have been successfully grown at 280-330 ¢ªC on Ge and Si by using RPCVD technique. It was demonstrated that the quality of epitaxial layers is dependent on the growth parameters, layer thickness and the quality of Ge virtual layer. It was found that a proper strain balance in the matrix during the epitaxy where the Si is adjusted carefully with the Sn flux improves the incorporation of Sn in Ge matrix. A similar improvement of Sn incorporation has been observed for phosphorous, boron and carbon doping in GeSn layers as well. This is explained by the compensation of the compressive strain caused by Sn by the tensile strain induced by Si to obtain the minimum energy in Ge matrix. This behavior was not observed for relaxed GeSn layers and Sn incorporation could be controlled only by the growth parameters. The thermal stability of GeSn is an important integration issue for device fabrication. The thermal stability of P- and B-doped GeSn layers was studied by rapid thermal annealing (RTA) in range of 400-600 ¢ªC and compared with intrinsic layers. The GeSn layers were stable up to 550 ¢ªC while the P-doped layers showed strain relaxation readily at 450 ¢ªC. The epitaxial quality of epi-layers was evaluated in terms of oxygen and water vapor contamination. The level of oxygen during epitaxy was as low as 10 ppb and the contamination amount was found as low as 1017cm-3.

In this study, a novel method using Focus Ion Beam (FIB) technique was applied to scale down Si1-xGexwires (x=0.27-0.57) to 20 nm width. Originally, the wires were processed by using I-line lithography and dry etching of SiGe on oxide (SGOI) substrates. The SGOI wafers were processed through condensation method where a SiGe/Si layer was grown in the beginning on SOI wafers and oxidized at 850-1050 °C. The shape of the nanowires (NWs) during the successive FIB cutting was examined by scanning electron microscopy (SEM) and the carrier transport through the NWs was checked by resistivity measurements. The contact resistance was reduced by Ni-silicide prior to metallization. The fabricated NWs were also suspended by tilting FIB. The results present the limitations and challenges of FIB technique to create NWs for advanced sensors and transistors.