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Techniques to reduce power well below regular transistor leakage in analog circuits are introduced. Key building blocks with super-cutoff transistor operation (i.e., $V_{\mathrm {GS}} < 0$ V) and pW-range consumption are demonstrated. Single-ended and fully differential versions of operational transconductance amplifiers (OTAs) are presented in several configurations, achieving 37-dB dc gain, 22.4-Hz gain-bandwidth product, and 25- $\mu \text{V}$ input-referred noise at 6.87 pW in 180-nm CMOS. For system-level demonstration, the proposed techniques are used in an optical wake-up receiver (WuRx) for light fidelity (LiFi) applications with 78-pW power. Continuous operation with a near-100% uptime is demonstrated when solely powered by an unregulated 1-mm2 solar cell down to 1 lx (moonlight) with no energy storage.

This special section of the IEEE Journal of Solidstate Circuits (JSSC) highlights outstanding papers presented at the 2023 IEEE International Solid-State Circuits Conference (ISSCC), which was held from February 19 to 23, 2023 in San Francisco, USA, under the conference theme “Building on 70 years of Innovation in Solid-State Circuit Design.” ISSCC is the foremost global forum for the presentation of advances in solid-state circuits and systems-on-a-chip (SoCs) and offers a unique opportunity for engineers working at the cutting edge of integrated circuit (IC) design and application. The conference includes several technical programs ranging from analog, digital, memory, wireline (WLN)/wireless, and power management circuits and systems with applications in various fields. This JSSC special section highlights selected papers from ISSCC, specifically on topics related to WLN circuits, digital circuit techniques (DCTs), digital architecture and systems (DASs), machine learning (ML) accelerators, and memory circuits.

In this work, a detection scheme signaling the occurrence of laser voltage probing (LVP) attacks in digital designs (e.g., cryptographic circuits) is introduced. The scheme comprises a standard cell-based photosensor fabric and distributed detectors. By construction, the scheme conforms the standard cell design discipline, restricted layout design rules, and commercial place and route tools. This allows seamless integration with automated design flows, and immediate adoption in a design-agnostic fashion. Hundred percentage time and area coverage is achieved for full protection against LVP attacks, while not requiring any calibration. Extensive attacks with $\sim 150$ h of characterization with a state-of-the-art LVP equipment on a 28-nm testchip demonstrate laser detection at both above- and below-bandgap wavelengths and, hence, even at the very low electron-hole pair generation rate of the former ones. Attacks to an advanced encryption standard (AES) core are shown to be flagged at any practical laser intensity and best-in-class true 220-nm laser spot. Low circuit activity confines its power to leakage, amounting to < 0.1% of the AES power. At the worst case, 150% area overhead is substantially lower in practical cases where the information-sensitive blocks are a portion of it (e.g., < 20% in an advanced reduced instruction set computer machines (ARM) Cortex-M4 processor with a secure AES accelerator). To the best of the authors’ knowledge, this is the first demonstration of a design-agnostic on-chip protection against LVP attacks with full-area coverage under unmodified manufacturing/packaging process.

The journey as Editor-in-Chief (EiC) of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI) from 2019 to 2022 has been exhilarating. Continuing the analogy with classical music concertos in recent editorials in this journal [1], [2], [3], some movements have been somewhat tempestuous in a rapidly changing world under a pandemic. Simultaneously, fundamental transformations have taken place in the semiconductor supply chain, as well as in our life and work style through increasingly distributed cooperation models (across continents, and from the office to the home office). Other movements have been highly rewarding thanks to the concerted effort (analogy intended) of a talented and rock-solid Editorial Board, whose precious contribution has led to relentless journal improvements in many respects. And, indeed, it has been a real pleasure to work with each and every one of the members of the TVLSI Editorial Board, whose commitment to excellence has brought the journal to new heights.

This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

The demand for distributed vision systems at an unceasingly larger scale requires the availability of sensor nodes able to execute high-level visual tasks (e.g., object detection for visual monitoring). Such tasks routinely entail the high computational cost of Convolutional Neural Networks (CNN), which conflicts with the tight power budget and memory capacity of sensor nodes at the edge. This paper introduces an approach to reduce the computational cost of object detection in CNN accelerators available in edge devices. The proposed approach induces additional feature map-level sparsity (i.e., computation skipping) at inference time by exploiting temporal correlation among frames. The proposed approach has an uncommonly favorable computation-memory tradeoff, as significant computation reduction is achieved at the cost of very small additional memory for the storage of intermediate features. As further benefits, no architectural changes or retraining are required, allowing immediate deployment in existing vision frameworks and suppressing the need for storing multiple models. Results show that the proposed TempDiff method achieves up to 37% computation reduction with 1.1% accuracy drop based on the SSD(VGG16) object detection network, under both VIRAT and ImageNet-VID datasets. Similarly, 18.3% (35.8%) computation reduction at 3.3% (3.2%) memory overhead, and 3.8% (6.8%) accuracy drop in YOLOv1 (VGG16) (SSD (VGG16)) is achieved under the CAMEL dataset. Furthermore up to 58% computation reduction with 2% accuracy drop and 3.7% memory overhead were achieved for YOLOv3-Tiny network under the ImageNet-VID dataset.

This paper aims to take stock of recent advances in the field of energy-quality (EQ) scalable circuits and systems, as promising direction to continue the historical exponential energy downscaling under diminished returns from technology and voltage scaling. EQ-scalable systems explicitly trade off energy and quality at different levels of abstraction and sub-systems, dealing with “quality” as an explicit design requirement, and reducing energy whenever the application, the task, or the dataset allow quality degradation (e.g., vision and machine learning). A general framework for EQ-scalable systems based on the concept of quality slack is presented along with scalable architectures. A taxonomy of techniques to trade off energy and quality, a VLSI perspective, and possible quality control strategies are then discussed. The state of the art is surveyed to put the advances in its different sub-fields into a unitary perspective, emphasizing the on-going and prospective trends. At the component level, the generality of the EQ-scaling concept is shown through several examples, ranging from logic to analog circuits, to memories, data converters, and accelerators. Interesting implications of the joint adoption of EQ scaling and machine learning are also discussed, suggesting that their synergy gives ample room for further energy and performance improvements. From a level of abstraction viewpoint, EQ scaling is discussed from the circuit level to architectures, the hardware-software interface, the programming language, the compiler level, and run-time adaptation. Several case studies are discussed to put EQ scaling in the context of real-world applications.

This Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of selected articles presented at the 2022 European Solid-State Circuits Conference (ESSCRIC) that was held in Milan, Italy, during September 19–22, 2022. The invited papers properly reflect the conference theme of “Intelligent electronics for a smarter and more inclusive human life.”

Sustained energy efficiency improvements have been instrumental for the vertiginous evolution of electronic systems with computing, sensing, communication and storage capabilities. Energy efficiency improvements are indeed crucial for continued increase in the performance under a limited power budget, reduced operating cost, as well as for untethering traditionally wired systems. This is indeed true for high-performance systems subject to heat removal limitations (e.g., server blades), as well as for operational cost considerations when the cost of electricity is a major fraction of the total cost, as in the case of datacenters [1], or the more recent crypto-currency mining endeavors [2]. Energy reductions are also critical in portable electronics, due to the limited thermal budget and battery energy availability. Similarly, energy reductions are essential in miniaturized energy-autonomous systems such as sensor nodes, hearables, wearables and others, due to their tightly constrained energy source [3]. Overall, energy efficiency improvements have historically permitted the continuous size down-scaling and lifetime extension of electronic systems (see, [4]).

In this article, a review of commercial devices on the edge of the Internet of Things (IoT), or IoT nodes, is presented in terms of hardware requirements. IoT nodes are the interface between the IoT and the physical world (e.g., sensor nodes). To this aim, we introduce a wide survey of existing devices made publicly available for the further analysis of trends and state of the art. This data-driven approach permits developing quantitative insight into the big picture of the current status of IoT nodes. The analysis shows that an order (ultimately two orders) of magnitude gap needs to be filled in terms of size, lifetime, and cost (energy efficiency) to ultimately make IoT nodes truly ubiquitous and trigger the widely expected exponential growth of the IoT ecosystem. Overall, this article presents a view from the edge of the IoT and a glimpse of its tipping point.

This paper investigates the impact of voltage scaling on energy and performance of STT-MRAM arrays under write access, which is well known to be energy critical. Simple analytical models of energy and delay are introduced to gain an insight into the energy-performance tradeoff at low voltages, and minimum-energy operation. The minimum-energy point is found to lie at voltages that are substantially higher than CMOS logic and memories. The impact of voltage scaling on the area-energy-performance tradeoff on most representative STT-MRAM bitcells is investigated and justified through the proposed models. Interestingly, bitcell area optimization is shown to enable 25%–40% energy savings compared to minimum-sized bitcells, when operating at low voltages. Results show that the write energy reduction achieved through voltage scaling strongly depends on the adopted bitcell, and was found to be up to 20%–30% in a 65-nm and 28-nm array. Voltage scaling is expected to become mainstream in STT-MRAM design, as promising approach to mitigate the well-known issue of large write energy consumption.