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We propose a two-terminal nanomagnetic memory element based on magnetization reversal of a perpendicularly magnetized nanomagnet employing a unipolar voltage pulse that modifies the perpendicular anisotropy of the system. Our work demonstrates that the presence of Dzyaloshinskii–Moriya interaction can create an alternative route for magnetization reversal that obviates the need for utilizing precessional magnetization dynamics as well as a bias magnetic field that are employed in traditional voltage control of magnetic anisotropy (VCMA)-based switching of perpendicular magnetization. We show with extensive micromagnetic simulation, in the presence of thermal noise, that the proposed skyrmion-mediated VCMA switching mechanism is robust at room temperature leading to extremely low error switching while also being potentially 1–2 orders of magnitude more energy efficient than state-of-the-art spin transfer torque-based switching.

The rapid increase in demand for computational and signal processing prowess calls for radical and revolutionary advances in reliable, energy-efficient, and dense computing architectures. The traditional complementary metal?oxide semiconductor (CMOS) field-effect-transistor-based processors are hardly up to the task because of the excessive energy dissipation that they are burdened with and the fact that CMOS is volatile and thereby inherently incapable of storing data indefinitely.

We propose and analyze a “spintronic/straintronic” reconfigurable equality bit comparator implemented with a nanowire spin valve whose two contacts are two-phase multiferroic nanomagnets and possess bistable magnetization. A reference bit is “written” into a stable magnetization state of one contact and an input bit in that of the other with electrically generated strain. The spin-valve’s resistance is lowered (raised) if the bits match (do not match). Multiple comparators can be interfaced in parallel with a magneto-tunneling junction to determine if an N-bit input stream matches an N-bit reference stream bit by bit. The system is robust against thermal noise at room temperature and a 16-bit comparator can operate at ∼743MHz while dissipating ∼28fJ per cycle. This implementation is more energy-efficient than CMOS-based implementations and the reference bits can be stored in the comparator itself without the need for refresh cycles or the need to fetch them from a remote memory for comparison. That improves reliability, speed and security.