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This report presents a design space analysis for the phase transition material (PTM)-augmented magnetic random-access memories (MRAMs) with separate read–write paths. PTM is augmented in parallel with the magnetic tunnel junction (MTJ), improving the read performance along with providing separate read–write paths. Compared to the standard MRAM, PTM-augmented design achieves up to $1.7 \times $ boost in cell tunnel magnetoresistance (CTMR), $1.2 \times $ increase in read disturb margin (RDM), and ${\sim }3.75 \times $ increase in sense margin (SM) at the cost of ${\sim }4.75 \times $ more power consumption. Here, we first discuss the operating region and biasing requirements to achieve performance improvement. Then, we thoroughly explore the design space to put more options on the table for choosing the material and device structure. Finally, we perform the variation analysis where we address the performance and variation immunity tradeoffs. We demonstrate a 1000-point Monte-Carlo analysis to illustrate the effects of process variations on the performance. With lower distinguishability and read stability, the variation tolerance of the design can be improved manifold employing device-circuit co-design methodology and vice versa.

Dynamic logic circuits suffer from leakage current during their evaluation period causing output voltage degradation. Although the keeper transistor is added to protect the output node from leakage, it comes with a considerable area and power penalty. In this article, we propose a novel design topology of a low-power dynamic logic circuit based on steep-switching hybrid phase transition FETs (Hyper-FETs). A Hyper-FET utilizes a phase transition material that exhibits selective insulator-to-metal transition enabling it to overcome the fundamental Boltzmann’s limit. The characteristic feature of the Hyper-FET also includes a higher ON–OFF ratio than the conventional counterpart. We utilize this unique advantage to alleviate the leakage issue in the dynamic circuits. We use a compact model of the phase transition material calibrated with experimental data of a single crystal VO2. For the baseline transistor, we use the predictive technology model of 14-nm FinFET. We comprehensively analyze the effects of different material parameters to explore the scope of further performance improvement. From our analysis, we deduce a range of insulating and metallic state resistance of the phase transition material (PTM) for optimum performance. We also examine the effect of process variation by performing the Monte Carlo variation analysis. Our analysis indicates that the leakage problem of the dynamic circuits is substantially improved as the phase transition material provides an additional high resistance with the pull-down network. We also observe that our design can outperform the conventional dynamic logic circuit even under random process variation.

Carbon NanoTube (CNT) channel promises near ballistic transport and is examined extensively for potential application in next-generation Nano-scale transistor. Cylindrical gate-all-around CNT field effect transistor (CNTFET) with semiconducting CNT S/D contacts and Schottky barrier CNTFET (SBCNTFET) are modeled numerically based on self-consistent solution of Poisson-Schrodinger equation with open boundary conditions within Non-Equilibrium Green's Function formalism considering coaxial symmetry. The effect of dielectric constant (k) and physical thickness of gate dielectric on transport characteristics of CNTFET and SBCNTFET are examined in this work. Gate capacitance, carrier injection velocity, current and therefore speed increases significantly with the inclusion of high k dielectric and decrease in thickness. SBCNTFET also shows better performance with thin high k dielectric layer. High trans-conductance and much lower Sub-threshold swing is visible with the inclusion of high k gate stack.

Due to ultra-long mean free path of Carbon nanotube (CNT), CNT field effect transistor (CNTFET) is supposed to operate in ballistic regime and therefore CNTEFT is under extensive research for its application in high performance devices replacing conventional silicon technology. Surrounding gate topology which is better performing than back-gated structure is considered for physical self-consistent modeling under NEGF framework using tight binding approximation. A detailed study of transport in ballistic regime reveals that equally doped source/drain (S/D) and channel with no potential gradient, short S/D about 5 nm, gate length close to 10 nm and (13, 0) zigzag CNT channel is optimum for designing high performance CNTFET.

Carbon NanoTube (CNT) channel promises near ballistic transport and is examined extensively for potential application in next-generation Nano-scale transistor. Cylindrical gate-all-around CNT field effect transistor (CNTFET) with semiconducting CNT S/D contacts and Schottky barrier CNTFET (SBCNTFET) are modeled numerically based on self-consistent solution of Poisson-Schrödinger equation with open boundary conditions within Non-Equilibrium Green’s Function formalism considering coaxial symmetry. The effect of dielectric constant (κ) and physical thickness of gate dielectric on transport characteristics of CNTFET and SBCNTFET are examined in this work. Gate capacitance, carrier injection velocity, current and therefore speed increases significantly with the inclusion of high κ dielectric and decrease in thickness. SBCNTFET also shows better performance with thin high κ dielectric layer. High trans-conductance and much lower Sub-threshold swing is visible with the inclusion of high κ gate stack.

Due to ultra-long mean free path of Carbon nanotube (CNT), CNT field effect transistor (CNTFET) is supposed to operate in ballistic regime and therefore CNTEFT is under extensive research for its application in high performance devices replacing conventional silicon technology. Surrounding gate topology which is better performing than back-gated structure is considered for physical self-consistent modeling under NEGF framework using tight binding approximation. A detailed study of transport in ballistic regime reveals that equally doped source/drain (S/D) and channel with no potential gradient, short S/D about 5 nm, gate length close to 10 nm and (13, 0) zigzag CNT channel is optimum for designing high performance CNTFET.