Search

Double data Rate type 4 memory (DDR4) die are commonly packaged in ball grid array (BGA) packages. The package solder balls develop fractures due to difference in the thermal coefficient of expansion of the package and printed circuit board (PCB). The intermittent behavior of the fracture is due to the momentarily opening of the solder joint due to vibration or the warpage of the package and the PCB. This intermittent behavior can result in no fault found phenomenon in memory systems. DDR4 response in the presence of an intermittent fracture depends on the location of defect. The defect can occur in clock, address, or data channel. A test fixture is used to show the ac coupling nature of fracture in BGA package solder ball. The intermittent change in the height of fracture is analyzed using 3-D electromagnetic model of the solder ball using high-frequency structure simulator (HFSS) software. HFSS model of the fractured solder ball is used along with DDR4 channel topology to compare the sensitivity of clock, address, and data channel response to intermittent fracture. It is shown that the data channel is most sensitive to intermittent fracture. DDR4 data mask violation occurs for even a small fracture height of 0.1 $\mu \text{m}$ . For clock channel, the eye degrades or becomes smaller as the fracture height increases from 0.1 to 3 $\mu \text{m}$ , but even for 3- $\mu \text{m}$ fracture height, clock eye diagram remains within DDR4 clock ±110 mV specification. For address channel, the eye degrades or becomes smaller when the height of fracture increases from 0.1 to 3 $\mu \text{m}$ . For fracture height of 3 $\mu \text{m}$ , DDR4 address ±65-mV input specification violation occurs. Address channel is more sensitive to intermittent fracture as compared to clock channel. The analysis shows that there is always intermittent error in data channel due to intermittent fracture, and there are more intermittent errors in address channel compared to clock channel.

Abstract: Single event upset (SEU) is mainly caused by neutrons in the terrestrial environment. In addition, SEU effects become more and more problematic as technology scales. It is, therefore, important to understand the SEU behaviors of semiconductor devices under neutron reactions. ANITA (atmospheric-like neutrons from thick target) in TSL (The Svedberg Laboratory), Sweden, resembles the neutron energy and flux spectrum to neutrons at the terrestrial level and are typically used to estimate the soft error rate (SER). On the other hand, the neutron energy and flux spectrum from the MC-50 cyclotron at KIRAMS (Korea Institute of Radiological & Medical Sciences) differs greatly from the atmospheric environment. The main objective of this work is finding the efficacy of the neutron beam at KIRAMS for a SEU analysis by using a comparative analysis; 55 nm SRAM is used to determine SEU difference under the beams at two different locations. Since MCU (multi-cell upset) is the dominant effect in emerging technologies with smaller critical charges, the MCU cross sections from the two different beam tests are compared.

Reliability is a critical issue for memories. Radiation particles that hit the device can cause errors in some cells, which can lead to data corruption. To avoid this problem, memories are protected with per-word error correction codes (ECCs). Typically, single-error correction and double-error detection (SEC-DED) codes are used. As technology scales, errors caused by radiation particles on memories tend to affect more than one cell—what is known as a multiple cell upset (MCU). To ensure that only a single cell is affected in each word, interleaving is used. With interleaving, cells that belong to the same word are placed at a sufficient distance such that an MCU will only affect a single cell on each word. The use of interleaving significantly increases the cost of the device. Also, determining the interleaving distance (ID) required to avoid MCUs causing double errors is not trivial. Typically, accelerated radiation experiments with a limited number of particle hits are used. They provide a lower bound on the required ID, but larger MCUs may occur with a low probability. But even if the percentage of such large MCUs is very low, the impact on reliability can be significant. This article presents a technique to mitigate the effects of large MCUs that is, those that exceed the ID, on memory reliability. The proposed approach is able to correct most double errors caused by large MCUs by exploiting the locality of the errors within an MCU.