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This article presents a comprehensive analytical framework for modeling p-GaN gate high-electronmobility transistors (HEMTs) based on rigorous solution of the Poisson and Schrödinger equations. It focuses primarily on the calculation of the 2-D electron gas (2DEG), voltage variation across the junction ( $\Delta V_j$ ), and AIGaN barrier ( $\Delta V_b$ ) for the entire range of forward gate bias until gate breakdown. Our model considers the impact of AIGaN barrier height saturation. In addition, we demonstrate our model with the engineered p-GaN doping profile that yields higher forward gate breakdown voltages. Gate capacitance and breakdown voltage have been modeled for both uniform and engineered p-GaN doping profiles. The viability and accuracy of the proposed model are demonstrated through comparisons with empirical measurement data and TCAD simulations.

The forward bias gate leakage current and forward gate breakdown voltage are important properties of p-GaN gate high-electron-mobility transistors (HEMTs). An engineered doping profile in the p-GaN layer results in a higher gate breakdown voltage and a lower forward bias gate leakage current. The use of such a technique puts additional requirements on the compact models that are used for these p-GaN gate HEMTs. An accurate compact model is needed, which considers a change in the doping profile in the p-GaN layer of these devices. This article reviews the relationship between the gate bias and the voltage drops at the different junctions in the gate structure (i.e., at the metal/p-GaN Schottky junction and the p-GaN/AIGaN/GaN junctions) considering an engineered doping profile. This relationship is then used to model the drain-source current ( $I_{\mathrm {DS}}$ ) and gate leakage current ( $I_G$ ). Three different regimes in the gate current have been considered in the model: Poole-Frenkel (PF) under low bias, thermionic emission (TE) in the medium bias range, and thermally assisted tunneling (TAT) at higher bias.

In this study, we investigate the reverse conduction diode mode failure mechanism in p-GaN gate high electron mobility transistors (HEMTs) using TCAD simulations and emission microscopy (EMMI). First, we observe a significant increase in gate leakage current when ${V}_{\text {DS}}$ is swept to −15 V while ${V}_{\text {GS}} =0$ V, indicating gate breakdown occurring with sufficient negative bias. Second, TCAD simulations are conducted to gain further insight into the failure locations and mechanisms. The simulations reveal high electric fields in the Schottky junction close to the interface between the metal and the p-GaN. This finding suggests that the gate region is likely the location leading to increased gate current and breakdown during the reverse conducting operation of the p-GaN gate HEMT. Lastly, EMMI measurements are performed on a device exhibiting high gate leakage current during reverse conduction diode mode operation. The EMMI results show bright spots in the gate region, which align with the failure location identified by the TCAD simulations. These results emphasize the importance of optimizing the Schottky/p-GaN junction to enhance the robustness of the p-GaN gate HEMT under reverse conduction diode mode operation.

In this work, the gate current characteristics are investigated to explain the threshold voltage shift in AlGaN/GaN high electron mobility transistors (HEMTs) with a p-GaN gate. First, the intrinsic gate current conduction mechanisms are identified: in the low bias range (2.5 V $ < {V}_{G} < $ 4 V), thermionic emission (TE) dominates in the AlGaN/GaN region, whereas in a higher bias range (4 V $ < {V}_{G} < $ 7 V) trap-assisted tunneling (TAT) is occurring in the Schottky/p-GaN region. Secondly, the threshold voltage shift of the stress phase is evaluated by applying a positive gate bias for various stress times. A consistent trap level with an activation energy of ${E}_{A}\sim $ 0.6 eV is found. In conclusion, a physical model explaining the negative ${V}_{\text {TH}}$ shift by considering TAT via hole transport is proposed.

We investigate the DC and dynamic characteristics of AlGaN/GaN Schottky barrier diodes (SBDs) and the diodes with a gated edge termination (GET‐SBD) fabricated on unintentional doped (UID) and carbon‐doped AlGaN buffers. The off‐state characteristics of diodes fabricated on UID buffer are dominated by buffer leakage and buffer breakdown voltage (BV) at higher reverse voltage (VRlarger than 300 V). An improvement in diode leakage and BV can be obtained by fabricating the GET‐SBDs on C‐doped buffers. A pronounced RONdegradation of the AlGaN/GaN SBDs and GET‐SBDs on carbon‐doped buffers was observed by dynamic pulsed I−Vcharacterization. This dynamic RONdegradation causes a clear forward current reduction for the AlGaN/GaN GET‐SBDs. From combined off‐state stress and current transient measurements on AlGaN/GaN SBDs, the collapsed current is recoverable and the RONdegradation is due to a temporary trapping mechanism occurring in the buffer. A distinct trap level of 0.57 eV from trap spectra has been extracted for the diode fabricated on C‐doped buffer, and the value was implemented in a TCAD simulator. The simulated results confirm a bulk trapping in the buffer layer for the SBD and show an additional trapping region in the GET‐SBD architecture.

This work provides an overview of our GaN-on-Si activity for high voltage applications. We will discuss the failure mechanisms of GaN-on-Si devices by electrical characterization and TCAD simulations. The main issues of the use of the Si as substrate are identified and addressed. A breakdown voltage as high as 1050 V and a specific on-resistance as low as 2 mOhm[?]cm2 have been achieved.

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work we demonstrate a technique of removing unwanted interfacial (silicon-) germanium oxide layers that form on the surface of SiGe depositions as soon as the wafers are removed from the deposition chamber and exposed to an O2 ambient.

This paper investigates the influence of the electrode spacing, chamber pressure, total gas flow, and dilution on the crystallinity, resistivity, uniformity, and stress of polycrystalline silicon-germanium (poly-SiGe) films grown by plasma-enhanced chemical vapor deposition (PECVD). Boron-doped PECVD SiGe films of thick are deposited on chemical vapor deposition layers from , , and precursors. The microstructure is verified by transmission electron microscopy and by X-ray diffraction. It was discovered that for constant temperature and deposition rate, the PECVD SiGe microstructure changes from completely amorphous to polycrystalline by increasing the electrode spacing and pressure due to reduced ion bombardment. A process window of an electrode spacing and pressure for the PECVD poly-SiGe deposition is thus identified based on a sheet resistance mapping method. Increasing the total gas flow dramatically improves the within-wafer crystallinity variation and further reduces the resistivity. Increasing the flow during PECVD shifts the stress from and further reduces the crystallinity variation over the wafer. In addition, the effect of changing the to ratio and the in situ boron doping by adding is also investigated. The findings in this paper are expected to facilitate the use of poly-SiGe in the above complementary metal oxide semiconductor (CMOS) microelectromechanical system (MEMS) applications.

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work an optimized process to deposit high quality crystalline poly-SiGe layers with low stress, low strain gradient and good within-wafer uniformity at a manufacturable throughput is developed. The process used to deposit the layers is based on a combination of CVD and PECVD SiGe depositions. Firstly, the CVD SiGe process has been extensively characterized to the extent that the influence of thickness, Ge concentration and B concentration on film stress and strain gradient is now well understood. Then the interaction between the PECVD SiGe and the underlying CVD layer has been investigated. This combined knowledge enables specific tailoring of the CVD-PECVD SiGe stack to give the desired strain gradient for a certain layer thickness.

In this work, a 2D-TCAD process simulation platform for high speed bipolar HBT devices with fT/fmax values exceeding 200GHz is presented. The process simulations implement a consistent model describing the diffusion behavior of boron and carbon in silicon and silicon germanium. In particular, the model successfully accounts for coupled diffusion of carbon and silicon point defects under several RTA conditions. The Kick-Out and Frank-Turnbull reactions model the carbon diffusion. Extended short-loop experiments under equilibrium and non-equilibrium conditions increased the accuracy of the simulations. It is shown that 2D-TCAD process simulations, calibrated with SIMS and TEM pictures, can be successfully complemented with the use of SSRM measurements, which provide emitter-base and collector- base junction delineation and two-dimensional carrier distributions. An excellent agreement in vertical and lateral electrical junction depths between SSRM measurements and the 2D-TCAD simulations validates the 2D process calibration.

To investigate the defects from the gate regrowth process, samples with and without regrowth p‐GaN process are fabricated by metalorganic chemical vapor deposition (MOCVD). The DC characteristics indicate larger gate leakage (Igs) between the GaN channel and the p‐GaN gate in the regrowth sample than in the nonregrowth counterpart. In addition, significant Si/O impurities are introduced by the regrowth process at the interface between channel and regrown AlGaN barrier. The low‐frequency noise (LFN) measurement and deep‐level transient spectroscopy (DLTS) are further carried out to investigate the defectivity at the AlGaN barrier and channel interface, giving a 2–3 times higher border trap density in the AlGaN barrier (depth ≈5 nm from the channel interface) and a 10 times increase in interface trap density at the channel interface, corresponding with a band of shallow levels E3 = Ec–0.02–0.15 eV. Three additional bulk traps E2/E5 (Ec–0.8 eV, σn=5×10−15cm2/ Ec–0.17 eV, σn=5×10−22cm2) and E4 (Ec–0.23 eV, σn=5×10−19cm2) are also found in the regrowth and nonregrowth samples, respectively. Their possible spatial locations and origins are discussed. The electrical properties of the defects originated from the p‐GaN gate regrowth process are studied by using deep‐level transient spectroscopy (DLTS) and low‐frequency noise (LFN) techniques. Several traps and high interface states corresponding to high gate leakage are found at channel regions. Their possible origins are discussed.

We propose a model for the gate capacitance of GaN-based trench-gate metal-oxide-semiconductor transistors, based on combined measurements, analytical calculations and TCAD simulations. The trench capacitance is found to be equivalent to four different capacitors, used to model the various regions with different doping and orientation of the semiconductor/dielectric interface. In addition, we demonstrate and explain the characteristic double-hump behavior of the G-D and G-DS capacitance of trench-MOSFETs. Lastly, a TCAD simulation results accurately reproduce the experimental data, thus confirming the interpretation on the double hump behavior, and providing insight on the electron density at the gate interface.

We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-assisted C-Vanalysis. Under positive gate stress, small negative Vthshifts (low stress) and a positive Vth shifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-trapping energy ?2.95 eV. UV-assisted CV measurements describe the distribution of states at the GaN/Al2O3interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors.

p-GaN gate enhancement mode power transistors were processed in a Si CMOS processing line on 200 mm Si(111) substrates using Au-free metallization schemes. Si/Ti/Al/Ti/TiN ohmic contacts were formed after full recessing of the AlGaN barrier, followed by a HCl-based wet cleaning step. The electrical performance of devices aligned to the $[11\bar{2}0]$ and the perpendicular $[1\bar{1}00]$ directions was compared. The ohmic contact resistance was decreased from 1 O*mm for the $[11\bar{2}0]$ direction to 0.35 O*mm for the $[1\bar{1}00]$ direction, resulting in an increase of the drain saturation current from 0.5 to 0.6 A/mm, and a reduction of the on-resistance from 6.4 to 5.1 O*mm. Moreover, wafer mapping of the device characteristics over the 200 mm wafer showed a tighter statistical distribution for the $[1\bar{1}00]$ direction. However, by using an optimized sulfuric/ammonia peroxide (SPM/APM) cleaning step, the ohmic contact resistance could be lowered to 0.3 O*mm for both perpendicular directions.

In this work, we demonstrate, for the first time, Al0.35GaN/GaN/Al0.25GaN double heterostructure field effect transistors on 200 mm Si(111) substrates. Thick crack-free Al0.25GaN buffer layers are achieved by optimizing Al0.75GaN/Al0.5GaN intermediate layers and AlN nucleation layers. The highest buffer breakdown voltage reaches 1380 V on a sample with a total buffer thickness of 4.6 µm. According to Van der Pauw Hall measurements, the electron mobility is 1766 cm2V-1s-1and the electron density is 1.16×1013cm-2, which results in a very low sheet resistance of 306±8 ?/square.

This work provides an overview of our GaN-on-Si activity for high voltage applications. We will discuss the failure mechanisms of GaN-on-Si devices by electrical characterization and TCAD simulations. The main issues of the use of the Si as substrate are identified and addressed. A breakdown voltage as high as 1050 V and a specific on-resistance as low as 2 mOhm⋅cm2 have been achieved.

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work we demonstrate a technique of removing unwanted interfacial (silicon-) germanium oxide layers that form on the surface of SiGe depositions as soon as the wafers are removed from the deposition chamber and exposed to an O2 ambient.

This paper investigates the influence of the electrode spacing, chamber pressure, total gas flow, and H2dilution on the crystallinity, resistivity, uniformity, and stress of polycrystalline silicon–germanium (poly-SiGe) films grown by plasma-enhanced chemical vapor deposition (PECVD). Boron-doped PECVD SiGe films of 1.6μmthick are deposited on 400nmchemical vapor deposition layers from SiH4, GeH4, and B2H6precursors. The microstructure is verified by transmission electron microscopy and by X-ray diffraction. It was discovered that for constant temperature and deposition rate, the PECVD SiGe microstructure changes from completely amorphous to polycrystalline by increasing the electrode spacing and pressure due to reduced ion bombardment. A process window of an electrode spacing and pressure for the PECVD poly-SiGe deposition is thus identified based on a sheet resistance mapping method. Increasing the total gas flow dramatically improves the within-wafer crystallinity variation and further reduces the resistivity. Increasing the H2flow during PECVD shifts the stress from −51to17MPaand further reduces the crystallinity variation over the wafer. In addition, the effect of changing the SiH4to GeH4ratio and the in situ boron doping by adding B2H6is also investigated. The findings in this paper are expected to facilitate the use of poly-SiGe in the above complementary metal oxide semiconductor (CMOS) microelectromechanical system (MEMS) applications.

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work an optimized process to deposit high quality crystalline poly-SiGe layers with low stress, low strain gradient and good within-wafer uniformity at a manufacturable throughput is developed. The process used to deposit the layers is based on a combination of CVD and PECVD SiGe depositions. Firstly, the CVD SiGe process has been extensively characterized to the extent that the influence of thickness, Ge concentration and B concentration on film stress and strain gradient is now well understood. Then the interaction between the PECVD SiGe and the underlying CVD layer has been investigated. This combined knowledge enables specific tailoring of the CVD-PECVD SiGe stack to give the desired strain gradient for a certain layer thickness.

In this work, a 2D-TCAD process simulation platform for high speed bipolar HBT devices with ƒT/ƒmaxvalues exceeding 200GHz is presented. The process simulations implement a consistent model describing the diffusion behavior of boron and carbon in silicon and silicon germanium. In particular, the model successfully accounts for coupled diffusion of carbon and silicon point defects under several RTA conditions. The Kick-Out and Frank-Turnbull reactions model the carbon diffusion. Extended short-loop experiments under equilibrium and non-equilibrium conditions increased the accuracy of the simulations. It is shown that 2D-TCAD process simulations, calibrated with SIMS and TEM pictures, can be successfully complemented with the use of SSRM measurements, which provide emitter-base and collector- base junction delineation and two-dimensional carrier distributions. An excellent agreement in vertical and lateral electrical junction depths between SSRM measurements and the 2D-TCAD simulations validates the 2D process calibration.