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High-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architecture for sparse matrix multiplication, and explores design space of the proposed architecture. The performance of various architecture configurations has been examined for input samples with similar characteristics. The proposed architecture has been implemented on Xilinx Kintex-7 FPGA using 32-bit single precision floating-point arithmetic and also in 8-bit, 16-bit and 32-bit fixed-point arithmetic formats. The effect of quantization in the proposed architecture has been analyzed extensively and the results have been reported. The performance of the proposed architecture has been compared with state-of-the-art implementations, and an improvement of 9.21% has been observed in the performance. [ABSTRACT FROM AUTHOR]

The goal is to make the approximation as close as possible to the actual function, typically with an accuracy close to that found in basic floating-point computer arithmetic. This is achieved by using high-degree polynomials and/or by narrowing the domain over which the polynomial should approximate the function. Domain narrowing can often be done by using various formulas to add or scale the functions being approximated. This paper consists of two main components, which are function approximation and function interpolation. Approximation of a function can be briefly described as the case when we replace a given function with another on a set. Interpolation can be defined as the requirement that the values of some two functions match on a certain set of arguments, that is, points. [ABSTRACT FROM AUTHOR]

In the bounded confidence model (BC-model) (Hegselmann & Krause 2002), period by period, all agents average over all opinions that are no further away from their actual opinion than a given distance ?, i.e., their 'bound of confidence'. With the benefit of hindsight, it is clear that we completely overlooked a crucial feature of our model back in 2002. That is for increasing values of ?, our analysis suggested smooth transitions in model behaviour. However, the transitions are in fact wild, chaotic and non-monotonic-as described by Jan Lorenz (2006). The most dramatic example of these effects is a consensus that breaks down for larger values of ϵ. The core of this article is a fundamentally new approach to the analysis of the BC-model. This new approach makes the non-monotonicities unmissable. To understand this approach, we start with the question: how many different BC processes can we initiate with any given start distribution? The answer to this question is almost certainly for all possible start distributions and certainly in all cases analysed here, it is always a finite number of ϵ-values that make a difference for the processes we start. Moreover, there is an algorithm that finds, for any start distribution, the complete list of ?,-values that make a difference. Using this list, we can then go directly through all the possible BC-processes given the start distribution. We can therefore check them for non-monotonicity of any kind, and will be able to find them all. This good news comes however with bad news. That is the algorithm that inevitably and without exception finds all the ?-values that matter requires exact arithmetics, without any rounding and without even the slightest rounding error. As a consequence, we have to abandon the usual floating-point arithmetic used in today's computers and programming languages. What we need to use instead is absolutely exact fractional arithmetic with integers of arbitrary length. This numerical approach is feasible on all modern computers. The new analytical approach and results are likely to have implications for many applications of the BC-model. [ABSTRACT FROM AUTHOR]

Due to the increasing popularity of application scenarios such as cloud computing, and the growing concern of users about the security and privacy of their data, information security and privacy protection technologies are facing new challenges. Consequently, Homomorphic Encryption (HE) technology has been developed. HE technology has evolved from Partially Homomorphic Encryption (PHE) to fully homomorphic encryption, from theory to practice Recently, the surge in machine learning applications has brought new challenges to HE technology. These applications require floating-point arithmetic numbers while adapting to a certain degree of precision loss, which has brought approximate homomorphic encryption (AHE) technology into the forefront of information security research. This work examines the development trajectory from PHE to AHE, and summarizes and analyzes the research works related to AHE from the three aspects: bootstrapping, improved precision, and variants. In addition, this work shows three different application scenarios of AHE from low level to high level, and combs the related works to present the readers with the latest application trend of AHE schemes. [ABSTRACT FROM AUTHOR]

Integer addition, being the fundamental process used in all other integer and floating point arithmetic operations, is the most important process used in computer systems and related applications. Many adder designs have been proposed in order to enhance the overall system performance. Approximation/speculation proves to be a very effective approach in leading to results faster than non-approximation techniques, though with its intrinsic drawback in having a potentially incorrect result. This paper proposes an approximate adder design with a very cost-effective error correction capability incorporated. In addition, with a built-in completion-detection mechanism, the proposed design is suitable for an asynchronous or variable-latency processing environment, and can deliver an expected completion time much shorter than all well-known parallel adders. [ABSTRACT FROM AUTHOR]

In this paper, we propose a generic pre-filtering method of point descriptors which addresses the confusion problem due to repetitive patterns. This confusion often leads to wrong descriptor matches and prevents further processes such as object recognition, image indexation, super-resolution or stereo-vision. Our method sorts keypoints by their unicity without taking into account any visual element but the feature vectors’s statistical properties thanks to a kernel density estimation approach. Both binary descriptors and floating point based descriptors are studied, regardless of their dimensions. Even if highly reduced in number, results show that keypoints subsets extracted are still relevant and our algorithm can be combined with classical post-processing methods. [ABSTRACT FROM AUTHOR]

The pair-precision technique, used to reduce round-off errors, was applied to the 6th-order symplectic integration method for integrating the equation of motion of the two-body problem. Analytical comparisons confirm that the implementation of pair-precision arithmetic operation functions reduces integration errors by a factor of 108 and a precision gain of around 20 digits along the orbit is obtained. Manipulated integration comes at the cost of approximately a 3.9-fold increase in CPU time, however, it is 2.1 times more efficient than using quadruple-precision computation. Integration with the pair-precision technique can be used for checking the validity and setting time limits for similar numerical calculations. More accurate calculations can extend the usefulness of predictions for evolutionary studies in the dynamics of the Solar System. [ABSTRACT FROM AUTHOR]

Hybrid multicore processors (HMPs) are poised to dominate the landscape of the next generation of computing on the desktop as well as on exascale systems. HMPs consist of general purpose GPU cores along with specialized cores and are expected to provide benefits to a wide spectrum of applications at significantly lower energy requirements per FLOP (FLoating-point Operations per Second). In this paper, we describe a comprehensive strategy for efficiently implementing a key kernel of spectral solvers on GPUs and HMPs consisting of CPU and GPUs. Our implementations represent significant computational improvements of the kernel on GPU. We also provide load balancing strategies for a combination of CPU and GPU cores. We show that depending upon whether performance or energy optimization is critical, separate load balancing strategies should be used on HMPs. We provide performance, power and energy evaluation as well as modeling and validation for a variety of CPU–GPU core combinations. [ABSTRACT FROM AUTHOR]

New hardware FPGA implementations for the efficient computations of division, natural logarithm and exponential function are proposed. The proposed implementations use generic floating-point adder and multiplier with small additional resources that are shared to compute more frequently used multiply and accumulate operations. Hardware sharing improved the resource utilization. The time of the computation has been reduced to only 6 clock cycles when the natural logarithm and exponential function are calculated. The division is calculated in 5 clock cycles. They are designed as technology independent high throughput computing cores with minimized memory requirements which can be used in higher numbers to significantly increased calculation speed in spectral processing. A new universal arithmetic floating-point unit is also proposed. [ABSTRACT FROM AUTHOR]

The need of complex multipliers in mathematics seems to be a very important aspect. The application used as a complex operation with respect to the real and imaginary numbers together. In many of the practical aspect the design substantiated to be a aiding hand for co-functionality units. Since to carry out the operations more correctly so as to elluct the technical peccadilloes. The results show that proposed FFT consumes very less resources in terms of slices, flip flops and multipliers to provide cost effective solution for DSP applications The proposed design has a desideratum for high efficacy eliciting structure in terms of accuracy. The device used in this proposed design is 7a30tcsg324-3. [ABSTRACT FROM AUTHOR]

Floating point numbers are an important data type in computation which is used extensively. Yet, many users do not know the standard which is used in almost all computer hardware to store and process these. In this article, we explain the standards evolved by The Institute of Electrical and Electronic Engineers in 1985 and augmented in 2008 to represent floating point numbers and process them. This standard is now used by all computer manufacturers while designing floating point arithmetic units so that programs are portable among computers. [ABSTRACT FROM AUTHOR]

This article presents the hardware implementation of the floating-point processor (FPP) to develop the radial basis function (RBF) neural network for the general purpose of pattern recognition and nonlinear control. The floating-point processor is designed on a field programmable gate array (FPGA) chip to execute nonlinear functions required in the parallel calculation of the back-propagation algorithm. Internal weights of the RBF network are updated by the online learning back-propagation algorithm. The on-line learning process of the RBF chip is compared numerically with the results of the RBF neural network learning process written in the MATLAB program. The performance of the designed RBF neural chip is tested for the real-time pattern classification of the XOR logic. Performances are evaluated by comparing results from the MATLAB through extensive experimental studies. [ABSTRACT FROM AUTHOR]

In comparison to dense matrices multiplication, sparse matrices multiplication real performance for CPU is roughly 5-100 times lower when expressed in GFLOPs. For sparse matrices, microprocessors spend most of the time on comparing matrices indices rather than performing floating-point multiply and add operations. For 16-bit integer operations, like indices comparisons, computational power of the FPGA significantly surpasses that of CPU. Consequently, this paper presents a novel theoretical study how matrices sparsity factor influences the indices comparison to floating-point operation workload ratio. As a result, a novel FPGAs architecture for sparse matrix-matrix multiplication is presented for which indices comparison and floating-point operations are separated. We also verified our idea in practice, and the initial implementations results are very promising. To further decrease hardware resources required by the floating-point multiplier, a reduced width multiplication is proposed in the case when IEEE-754 standard compliance is not required. [ABSTRACT FROM AUTHOR]

Copyright of Informatica (03505596) is the property of Slovene Society Informatika and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

ASIC implementation of a high speed multiplier using a high accuracy oating point logarithmic number system is reported in this paper. The most popularly used techniques for computing logarithmic calculations for digital signal processors are: Lookup table based implementation, polynomial approximation, and Taylor series expansion. But, all these techniques suffer from low accuracy, due to the choice of having only lower order terms of the expanded series. In the present work, logarithmic conversion is implemented by a oating point (IEEE-754 single precision) converting methodology, thereby eliminating series expansion, which eventually results in high accuracy. The improvement in speed, by avoidance of carry propagation, was achieved through Canonical Signed Digit Code (CSDC) implementation, while the high accuracy was achieved through an error minimization circuitry especially designed for this purpose. The functionality of these circuits was checked, and performance parameters, like propagation delay and dynamic power consumption, were calculated by spice spectre using 90 nm CMOS technology. The propagation delay and power consumption of the resulting (128 × 128) bit multiplier (divider) was only ~ 93 ns and ~ 80 mW, respectively, for a layout area of ~ 25mm2. This implementation offered a significant improvement in terms of accuracy, delay and power from those reported earlier. [ABSTRACT FROM AUTHOR]

A new technique for radix-3 FFT butterfly unit based on floating-point operation is proposed. The aim of the new design is to reduce the hardware resources. First, compatible scaling is used to solve the multiplication. Let the scale factor of √3 be 223, so the multiplication with √3 is replaced by several fixed-point additions. By theoretical analysis, the proposed method decreases the numbers of adders and registers. By contrast, the proposed design reduces one fixed-point adder and two 48-bit registers. In additional, a structure of radix-3 FFT butterfly unit is adopted and in this structure, the number of multiplications with a real data is reduced from 4 to 2. Experimental results show that the proposed method indeed reduces the hardware resources, which plays an important role in decreasing the resources of radix-3 FFT. [ABSTRACT FROM AUTHOR]

Abstract: A large variety of data mining and machine learning techniques are applied to a wide range of applications today. There- fore, there is a real need to develop technologies that allows data analysis while preserving the confidentiality of the data. Secure multi-party computation (SMC) protocols allows participants to cooperate on various computations while retaining the privacy of their own input data, which is an ideal solution to this issue. Although there is a number of frameworks developed in SMC to meet this challenge, but they are either tailored to perform only on specific tasks or provide very limited precision. In this paper, we have developed protocols for floating point arithmetic based on secure scalar product protocols, which is re- quired in many real world applications. Our protocols follow most of the IEEE-754 standard, supporting the four fundamental arithmetic operations, namely addition, subtraction, multiplication, and division. We will demonstrate the practicality of these protocols through performing various statistical calculations that is widely used in most data analysis tasks. Our experiments show the performance of our framework is both practical and promising. [Copyright &y& Elsevier]

In this paper, we present the LFSR Test Vector Generator for Floating Point Arithmetic Unit (FPAU); it improves the performance of multimedia processing with low hardware cost. Here, we focused on a decimal floating point unit which consists of adder and subtractor for high speed computing. It takes input as binary real numbers, converts them into single precision IEEE 754 format floating point numbers, performs operations and gives the output with high precision. We used Guard bit, Sticky bit and Round bit to get output with good precision. At last, we tested the unit by the values from LFSR. The FPAU was modeled and synthesized in Verilog HDL and LFSR was implemented 90nm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, we present the LFSR Test Vector Generator for Floating Point Arithmetic Unit (FPAU); it improves the performance of multimedia processing with low hardware cost. Here, we focused on a decimal floating point unit which consists of adder and subtractor for high speed computing. It takes input as binary real numbers, converts them into single precision IEEE 754 format floating point numbers, performs operations and gives the output with high precision. We used Guard bit, Sticky bit and Round bit to get output with good precision. At last, we tested the unit by the values from LFSR. The FPAU was modeled and synthesized in Verilog HDL and LFSR was implemented 90nm CMOS technology. [ABSTRACT FROM AUTHOR]

Abstract: In content-based image retrieval (CBIR) application, a large amount of floating-point data is processed. Among various low-level features, color is an important feature and represented in the form of histogram. It is essential that features required to be coded in such a way that the storage space requirement is low and processing speed is high. In this paper, we propose an encoding approach using Golomb-Rice coding, which effectively codes the floating point bin values of the color histogram. The floating point values are converted into integer values using preprocessing steps. The encoded histogram is finally represented in the form of sparse matrix and XOR based bitwise comparison is used as similarity measure to calculate the distance between the encoded and query histogram in the feature space. Based on the number of 1''s, the retrieved list is ranked and the relevant images are presented. This approach is tested in CBIR application and the precision of retrieval is encouraging compared to the original color histogram and the average bit length is very low besides having fast retrieval time. [Copyright &y& Elsevier]

Abstract: LU factorization is the most computationally intensive step in solving systems of linear equations. By obtaining first the LU factorization of the coefficient matrix, we then may readily solve the system using backward substitution. The computational cost of LU factorization in terms fioating point operations is cubic. There are various efforts to improve the performance of LU factorization. We propose a multi-core multi-GPU hybrid LU factorization algorithm that leverages the strengths of both multiple CPUs and multiple GPUs. Our algorithm uses some of the CPU cores for panel factorization, and the rest of the CPU cores together with all the available GPUs for trailing submatrix updates. Our algorithm employs both dynamic scheduling and static scheduling. Experiments show that our approach reaches 1134 Gflop/s with 4 Fermi GPU boards when combined with the total of 48 CPU cores from AMD. This is the first time such level of performance have been reported in a shared memory environment. Execution trace shows that our code also achieves good load balance and high system utilization. [Copyright &y& Elsevier]

Abstract: In the multi-peta-flop era for supercomputers, the number of computing cores is growing exponentially. However, as integrated circuit technology scales below 65 nm, the critical charge required to flip a gate or a memory cell has been reduced and thus causing higher soft error rate from cosmic-radiations. Soft errors affect computers by producing silently data corruption which is hard to detect and correct. Current research of soft errors resilience for dense linear solver offers limited capability when facing large scale computing systems, and suffers from both soft error and round-off error due to floating point arithmetic. This work proposes a fault tolerant algorithm that recovers the solution of a dense linear system Ax = b from multiple spatial and temporal soft errors. Experimental results on Cray XT5 supercomputer confirm scalable performance of the proposed resilience functionality and negligible overhead in solution recovery. [Copyright &y& Elsevier]

Abstract: Embedded CPUs typically use much less power than desktop or server CPUs but provide limited or no support for floating-point arithmetic. Hybrid reconfigurable CPUs combine fixed and reconfigurable computing fabrics to balance better execution performance and power consumption. We show how a Stretch S6 hybrid reconfigurable CPU (S6) can be extended to natively support double precision floating-point arithmetic. For lower precision number formats, multiple parallel arithmetic units can be implemented. We evaluate if the superlinear performance improvement of floating-point multiplication on reconfigurable fabrics can be exploited in the framework of a hybrid reconfigurable CPU. We provide an in-depth investigation of data paths to and from the S6 reconfigurable fabric and present peak and sustained throughput as a function of wide registers used and total operand size. We demonstrate the effect of the given interface when using a floating-point fused multiply-accumulate (FMA) SIMD unit to accelerate the LINPACK benchmark. We identify a mismatch between the size of the S6s reconfigurable fabric and the available interface bandwidth as the major bottleneck limiting performance which makes it a poor choice for scientific workloads relying on native support for floating-point arithmetic. [Copyright &y& Elsevier]

Copyright of Electronics & Electrical Engineering is the property of Electronics & Electrical Engineering and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The paper deals with various parallel platforms used for high performance computing in the signal processing domain. More precisely, the methods exploiting the multicore central processing units such as message passing interface and OpenMP are taken into account. The properties of the programming methods are experimentally proved in the application of a fast Fourier transform and a discrete cosine transform and they are compared with the possibilities of MATLAB's built-in functions and Texas Instruments digital signal processors with very long instruction word architectures. New FFT and DCT implementations were proposed and tested. The implementation phase was compared with CPU based computing methods and with possibilities of the Texas Instruments digital signal processing library on C6747 floating-point DSPs. The optimal combination of computing methods in the signal processing domain and new, fast routines' implementation is proposed as well. [ABSTRACT FROM AUTHOR]

Abstract: Many languages viz. COBOL, C, C++, Java, Python etc have emerged and evolved in the arena of formal systems over the past few decades,. Programming language processors are designed to convert a high level language written source code to equivalent object code viz. interpreter, compiler etc. There exist variations in programming paradigm, like procedure-oriented, object–based, object oriented, low-level and logic/invariant. But irrespective of the programming methodology, trivial issues related with errors or bugs are often faced. Bug is always undesired to occur. So, need for a debugger embedded to compiler exists. Almost every language has a debugger module mostly dependent on involvement of developers. But again programmer needs to eliminate errors from the source code manually by dint of debugger module. The presented approach, a framework is proposed in which the elimination of the errors from the program source code is developer independent. The function of this module is to remove of the error one by one and to generate a debugged i.e. error-free form of the whole program. Then we will execute than debugged form of the source code to obtain our intended result. The framework is well-documented in the works of Gupta et al. . However, the issue ‘if the debugged form of the source code is non-unique i.e. more than one debugged form is found’ is not widely circulated in the literature. Effort has been made to get rid of the problems. The work presents an auto-debugger module in the interdisciplinary area of compiler design and machine intelligence that can take care of non-unique errors. The concept is accompanied by a developed compiler named SHARP. SHARP facilitates use of variable length of data type and further a framework of floating-point arithmetic different from the standard practice of mantissa-exponent scheme. It is expected that this will navigate the study of automated language processor to a new horizon. [Copyright &y& Elsevier]

Abstract: This study identifies a factor that leads to a bias in estimating the probability of informed trading (PIN), a widely-used microstructure measure. It is shown that, along with the numerical maximization of the likelihood function for PIN, the floating-point exception (i.e., overflow or underflow) may eliminate feasible solutions to the actual parameters in the optimization problem. Approximately 44% of PIN estimates for recent stock market data may have been subject to a downward bias that is more pronounced for active stocks than for inactive stocks. This study develops a remedy to mitigate the resulting bias. [Copyright &y& Elsevier]

Abstract: In this paper we investigate how stencil computations can be implemented on state-of-the-art general purpose graphics processing units (GPGPUs). Stencil codes can be found at the core of many numerical solvers and physical simulation codes and are therefore of particular interest to scientific computing research. GPGPUs have gained a lot of attention recently because of their superior floating point performance and memory bandwidth. Nevertheless, especially memory bound stencil codes have proven to be challenging for GPGPUs, yielding lower than to be expected speedups. We chose the Jacobi method as a standard benchmark to evaluate a set of algorithms on NVIDIA''s latest Fermi chipset. One of our fastest algorithms is a parallel wavefront update. It exploits the enlarged on-chip shared memory to perform two time step updates per sweep. To the best of our knowledge, it represents the first successful applicationof temporal blocking for 3D stencils on GPGPUs and thereby exceeds previous results by a considerable margin. It is also the first paper to study stencil codes on Fermi. [Copyright &y& Elsevier]

Abstract: There is growing interest in performing ever more complex classification tasks on mobile and embedded devices in real-time, which results in the need for e_cient implementations of the respective algorithms. Support vector machines (SVMs) represent a powerful class of nonlinear classifiers, and reducing the working precision represents a promising approach to achieving e_cient implementations of the SVM classification phase. However, the relationship between SVM classification accuracy and the arithmetic precision used is not yet su_ciently understood. We investigate this relationship in floating-point arithmetic and illustrate that often a large reduction in the working precision of the classification process is possible without loss in classification accuracy. Moreover, we investigate the adaptation of bounds on allowable SVM parameter perturbations in order to estimate the lowest possible working precision in floating-point arithmetic. Among the three representative data sets considered in this paper, none requires a precision higher than 15 bit, which is a considerable reduction from the 53 bit used in double precision floating-point arithmetic. Furthermore, we demonstrate analytic bounds on the working precision for SVMs with Gaussian kernel providing good predictions of possible reductions in the working precision without sacrificing classification accuracy. [Copyright &y& Elsevier]

Logarithmic number system (LNS) arithmetic is more efficient than floating-point arithmetic in computing complex arithmetic functions with consecutive multiplication, division, and powering operations. However, computation of the log2 (1 ± 2-v) function in LNS addition/subtraction will cost a large hardware, especially when the operand word length is large. Direct computation of the logarithmic function log2 (1 ± 2-v) in LNS addition/subtraction is a promising method for the practical implementation of large word-length LNS arithmetic. Two most important operations in this method are the exponent and logarithm computations. In this paper, we have analyzed the maximum errors of the LNS addition/subtraction that is computed by using the direct computation method. From our analysis, we found that the precision requirement of the exponent computation in the direct computation method should be at least the precision of the double word length of the LNS operands. This large precision requirement will result in a large hardware cost for the exponent computation. [ABSTRACT FROM AUTHOR]

To enable floating-point (FP) signal processing applications in low-power mobile devices, we propose lightweight floating-point arithmetic. It offers a wider range of precision/power/speed/area trade-offs, but is wrapped in forms that hide the complexity of the underlying implementations from both multimedia software designers and hardware designers. Libraries implemented in C++ and Verilog provide flexible and robust floating-point units with variable bit-width formats, multiple rounding modes and other features. This solution bridges the design gap between software and hardware, and accelerates the design cycle from algorithm to chip by avoiding the translation to fixed-point arithmetic. We demonstrate the effectiveness of the proposed scheme using the inverse discrete cosine transform (IDCT), in the context of video coding, as an example. Further, we implement lightweight floating-point IDCT into hardware and demonstrate the power and area reduction. [ABSTRACT FROM AUTHOR]