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A modular voltage equalizer can be used in a wide variety of applications without changing the module design. However, the modularization of an equalizer topology often involves slow intermodule equalization, additional energy loss, and cost. A study on available modularization techniques shows that transformer-based equalizers offer simple and low-cost modularization methods. Conversely, the transformer-less equalizers can offer a more compact design, but their modularization methods suffer from either high complexity and loss, or slow intermodule equalization speed. In this work, one two-winding transformer is introduced into a transformer-less equalizer module to leverage the modularization benefits of transformer isolation while still achieving a more compact design than transformer-based equalizers. The proposed direct modularization method achieves fast intermodule equalization and fixed design for a variety of applications with a small increase in cost and size. The proposed method is implemented on a transformer-less equalizer and its effectiveness is validated experimentally with a three-module prototype.

Switching frequency is utilized as a degree of freedom in digital control strategies for power converters. In addition to carrier-based schemes, quadrature oscillators offer an alternative method for the generation of variable frequency switching pulses. In this article, amplitude instability in a computationally simple digital quadrature oscillator is analyzed. Algorithms for stabilizing the oscillator are developed based on this. Further implementation issues arising are addressed and a systematic comparison to carrier-based schemes is executed. It is shown that the proposed approach can be implemented with only four additions and four comparison steps without resorting to multiplication. The studies are validated in system simulation and experiments on a commercial field programmable gate array board.

A Point-on-Wave Fault Branch (PWFB) can be used to create various balanced and unbalanced electrical faults in an experimental testbed. Utilizing fully controllable semiconductor switches, the PWFB offers unique advantages of precise fault creation and clearance at user-defined angles relative to the input reference voltage. In contrast to the traditional fault branches utilizing Four-Quadrant Switches (FQSes), which necessitate one or two capacitors or surge arresters for over-voltage protection per FQS, this paper proposes a PWFB design that incorporates a single capacitor to protect all FQSes from over-voltage conditions during various fault scenarios. The proposed method significantly reduces the overall size and cost of the PWFB. Furthermore, the paper introduces a novel FQS configuration, leveraging commercially available half-bridge Insulated Gate Bipolar Transistor (IGBT) and power diode modules. A PWFB prototype is developed and rigorously tested on two distinct systems: (i) a 5 kVA grid-connected transformer with an inductive load and (ii) a Single-Machine Infinite Bus (SMIB) system. These experiments demonstrate the single capacitor's efficacy in clamping peak voltages and validate the PWFB's ability to generate consistent and reproducible faults while protecting all associated FQSes.

This paper presents an analysis of asymmetrical modular phase-shifted full-bridge (PSFB) converters in input-parallel output-parallel (IPOP) configuration for high-current and high-power applications and proposes a new control method that enhances system efficiency. The performance of the asymmetric IPOP-PSFB system under nonideal parametric mismatches in transformer turns-ratio, filter and leakage inductances is studied under various control methods. The widely employed common duty ratio scheme (CDR) and its implications on power sharing among the modules are compared with an independent duty ratio control (IDC) scheme. Contrary to the equal power-sharing scheme among symmetrical modules, a Lagrangian loss optimal load-sharing (L$^{2}$OL) technique leveraging the parametric asymmetry among the modules is proposed. This technique improves the overall system efficiency by appropriately loading individual PSFB modules. The proposed control method improves light load efficiency by 5.7%, mid load efficiency by 0.5% while preserving the full load efficiency compared to that obtained from equally loaded symmetrical modules. The effect of parametric asymmetry on power sharing using CDR and IDC schemes and power loss in symmetrical and L$^{2}$OL strategies are compared based on analysis and simulations. This is validated on a laboratory hardware prototype comprising two PSFB modules, for a 2 $\text{kW}$, 400 $\text{V}$ to 48 $\text{V}$ system.

Second-harmonic ($2\omega$) filter is a critical constituent in the single-phase power conversion system and continues to trigger significant research interest. Due to the design and performance trade-offs between passive and active filters, hybrid filters have emerged as an attractive solution that combines the desired features. Moreover, in an existing system, re-tuning, retrofitting, or replacement of the passive filters becomes inevitable due to degraded filter characteristics with parameter drifts. Considering these requirements, an easily integrable active circuit, named solid state tuning restorer (SSTR), is proposed in this work to enhance the performance of an existing LC filter. Along with SSTR, the second-harmonic tuned passive LC filter forms a hybrid filter with adjustable characteristics capable of maintaining the tuned state over a range of operating frequencies and LC parameters. The low volt-ampere (VA) rating of SSTR, being less than 2% of the main converter, facilitates easy integration with the existing dc bus LC filter. Even in case of SSTR failure, the configuration offers a graceful degradation in the filter characteristics without disrupting the main converter. Thus, it improves the performance of an existing second-harmonic LC filter while not compromising its reliability. The operation, design constraints, and control methodology of the proposed SSTR are discussed, and the performance is validated through experiments on a hardware prototype.

The LCC resonant converter with a capacitive output filter is a popular topology for variable load applications, although the simultaneous design requirements of wide load range, soft switching, and low conduction loss are not clearly tackled in available design strategies. In this article, the existing time-domain analysis of the converter is extended in a normalized design-oriented fashion. The proposed extension to boundary modes lends itself to the derivation of critical converter characteristics such as the soft switching range. A dimensionless converter and load characteristic-based design algorithm with parameter decoupling is developed to meet the load requirements. The design algorithm reduces the converter rms current while meeting practical requirements of zero-voltage switching and constraints on switching frequency across the load range. The proposed design method is validated using circuit simulations incorporating series dissipative nonidealities and the transformer magnetizing inductance, and also on a 160-W laboratory prototype with switching frequency within the designated limits and $>96\%$ experimental efficiency.

Active second-harmonic ( $2\omega $ ) filters have become an integral technology for single-phase power converters in high-power density designs. The series-stacked buffer (SSB) has emerged as an attractive topology among the existing solutions due to its low power, high efficiency, and compact design. However, one of the challenges in adopting SSB lies in its control, where hysteresis current control has been adopted conventionally. This results in a wide variation in the switching frequency, making the digital control implementation and filter design complex. On the other hand, fixed-frequency pulsewidth modulation (PWM) control necessitates developing a model for the systematic controller design to ensure stability and desired filtering performance. The assumption of SSB modeled as a second-harmonic current source, independent of the dc bus circuit components, fails to capture the dc bus loading effect on the SSB. In this work, a dynamic model of SSB is developed where the main dc bus and its passive elements are considered. The derived model enables a systematic approach for the controller design while ensuring the desired $2\omega $ filtering. The stability limits and parameter sensitivities of the model are studied analytically and in simulations. The analytical model is validated, and the proposed controller performance and stability limit are verified experimentally on a hardware prototype. A video demonstrating the transition from stable to unstable operation is provided.

Flexible characteristics, tunable parameters, and improved power density are the desired attributes that have led to widespread research on active capacitors and inductors (ACI) in power conversion systems. However, the two-terminal realisation of ACI is challenging due to different trade-offs between power density, device stress, and reliability of the added components. Moreover, the requirement of handling second-harmonic ripple makes bulk electrolytic capacitors nearly indispensable in two-terminal ACIs. Thus, the scope of power density improvement becomes constrained. Hence, active capacitors requiring minimum or no bulk dc capacitance are seen as an attractive technology in recent literature. However, such solutions can mimic either inductive or capacitive behaviour with a single converter unit, restricting their adaptability across different applications. This limitation is addressed in this work with the proposed unified active capacitor and inductor (UACI), realised without any bulk dc capacitor. It emulates variable capacitance and inductance while offering a smooth transition from one characteristic to another. High effective impedance due to a small susceptance at the transition duty prevents undesirable current overshoot during the transition. A laboratory-scale prototype of the proposed ACI is fabricated, and the hardware is verified up to $\pm$450 VAR.

Increasing electrical energy demand in tandem with the requirement to ensure good levels of load power quality is a growing need. Traditionally, power electronics-based static uninterruptable power supplies and diesel gensets have been employed to ensure continuity of power supply to tackle power interruptions. AC micro-grids (MG) have attracted significant attention recently owing to their ability to address these issues on a macro-scale with the aid of clusters of on-site heterogeneous micro-sources along with suitable energy storage systems. However, these systems are not necessarily large and complex networks, and it is observed that even simpler systems of smaller ratings functionally qualify as AC micro-grids. To meet the objectives of achieving high performance at low cost, three types of power conversion technologies are proposed for AC micro-grids: (1) reconfigurable battery/grid-tied inverter (RBGTI); (2) dual-mode converter (DMC); and (3) active-phase converter (APC), which enhance power quality and efficiency of energy access. RBGTI and DMC are photo-voltaic (PV) inverter-based MG technologies that ensure efficient solar energy utilization even in the absence of the power grid, unlike conventional PV grid-tied inverters. APC is a motor-drive technology that enables safe interconnection of three-phase motors on single-phase grids or micro-grids while ensuring high levels of efficiency and load power quality when compared to the conventional double-conversion drive systems. These technologies are particularly relevant in the Indian scenario, where there are grid power quality and availability are significantly different from that of other parts of the world. A high-performance General-Purpose Inverter Stack platform developed in the laboratory is employed to realize and verify the performance of the proposed power conversion technologies.

Improved SRF-PLL using moving average filter (MAF) is an established phase locked loop method for operation of three phase grid connected VSI under non-ideal grid conditions. This three phase PLL method can also be used in a single phase system without changing its structure. Hence, in applications where the grid connected VSI has to work under both three phase and single phase source, a MAF-SRF-PLL is useful for maintaining proper synchronism. In this letter, first an already available design of three phase MAF-SRF-PLL has been evaluated experimentally under various single phase grid condition in terms of unit vector quality. Next the same PLL structure has been tested for situations where circuit reconfiguration from three phase to single phase and vice versa are necessary.

The output of a solar photovoltaic (PV) system can be predicted using a parameterized model. The parameters can be obtained from the datasheet of the panel or from the measured current-voltage (I-V) characteristics. Measurement-based parameter estimation is shown to provide better results, as compared with the datasheet-based method. This effect magnifies for older panels due to the deterioration of panel characteristics with time, leading to a deviation from the datasheet specifications. Least-squares minimization is applied on the measured data using the Levenberg-Marquardt algorithm (LMA), trust region reflective Newton, and steepest descent optimization, which are compared on the basis of accuracy and speed. Low computational complexity and high parameter accuracy is ensured by introducing a novel sequential parameter estimation, in which two of the parameters are analytically evaluated, and a separate sequential evaluation of the shunt resistance parameter is performed. The predicted maximum power from the proposed method matches the experimental measurements with high accuracy.

AbstractInverters are required to convert the dc power from photovoltaic panels to ac. In grid connected inverters, the ac output is directly fed into the electric grid. In this paper, a high-frequency transformer based inverter topology is presented. This leads to a very compact inverter. The modulation of this inverter with a lossless snubber circuit is proposed. Proposed modulation eliminates the over-voltage spikes due to transformer leakage inductance. Commutation of the leakage inductance energy with this modulation is also discussed. The performance of the inverter with the proposed modulation is validated using simulation and experimental results.