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Thickness of buffer layers affects performance of flexible polycrystalline silicon thin film transistors (TFT). A thicker buffer SiO2film demonstrates better endurance to thermal expansion stress from the polyimide substrate. However, the thickness of buffer SiO2film would causes the variation of optimal excimer laser annealing (ELA) crystallization condition. In addition, the simulation results shows that the non-uniform stress in the gate insulator is more pronounced near the poly-silicon/gate insulator edge and at the two sides of the poly-silicon protrusion. It would affect the stability results and device performance. By optimization the process condition, the device would still have good device performance after operating under high temperature (60 ?) and long period of time (500hrs).

The composition of buffer layer would be played a key role to affect the electrical performance and the reliability of the self-aligned top-gate a-IGZO TFTs. In this work, the threshold voltage shift (?Vth) of the device could be less than ±1V under positive and negative bias thermal illumination stress.

The surface morphology in polycrystalline silicon (poly-Si) film is an issue regardless of whether conventional excimer laser annealing (ELA) or the newer metal-induced lateral crystallization (MILC) process is used. This paper investigates the stress distribution while undergoing long-term mechanical stress and the influence of stress on electrical characteristics. Our simulated results show that the nonuniform stress in the gate insulator is more pronounced near the polysilicon/gate insulator edge and at the two sides of the polysilicon protrusion. This stress results in defects in the gate insulator and leads to a nonuniform degradation phenomenon, which affects both the performance and the reliability in thin-film transistors (TFTs). The degree of degradation is similar regardless of bending axis (channel-length axis, channel-width axis) or bending type (compression, tension), which means that the degradation is dominated by the protrusion effects. Furthermore, by utilizing long-term electrical bias stresses after undergoing long-tern bending stress, it is apparent that the carrier injection is severe in the subchannel region, which confirms that the influence of protrusions is crucial. To eliminate the influence of surface morphology in poly-Si, three kinds of laser energy density were used during crystallization to control the protrusion height. The device with the lowest protrusions demonstrates the smallest degradation after undergoing long-term bending.

This paper reports the effect of off-state stress on the LTPS TFTs on plastic substrates. In this study, by giving LTPS devices off-state bias stress one millisecond, it could get an excellent off-state current from 50 pA to 2pA when device operate at VGS=+7V, VDS=-5.1V. This could be attributed to electron trapping occur in gate insulator could reduce off-state electric field near to drain region.

This study examines the dependence of light-accelerated instability on bias and environment in amorphous indium-gallium-zinc-oxide thin film transistors. When device is in vacuum ambient, the threshold voltage of device after negative gate bias illumination stress (NBIS) showed bias-dependent electrical degradation behavior. However, experimental results show the degradation of electrical characteristic in a-IGZO devices does not only rely on the charge trapping mechanism for NBIS. During NBIS in oxygen, moisture-simulated and atmosphere ambient, the negative shift in electrical characteristic is suppressed when compared to that in vacuum. This implies that the adsorbent gas species in the surrounding environment dominates the electrical characteristic degradation of devices during NBIS, which leading the change of dominant mechanism from photon-created carrier trapping to adsorbed/desorbed gas phenomenon.

This study investigates the influence of a photo-thermal treatment on the electrical characteristics and bias-induced instability of amorphous Zn-Sn-O thin film transistors. Sequences of measurements made in both vacuum and oxygen ambient reveal the most pronounced threshold voltage (VT) shift, i.e., the highest sensitivity of oxygen, occurs in a device with photo-thermal-treatment. After gate-bias stress in vacuum, the treated device shows less VTshift than that untreated, which can be attributed to residual adsorbed gas molecules on the backchannel. Thus, the proposed photo-thermal-treatment should be conducted before depositing a passivation layer to increase the reliability of devices after stress.

This paper investigates anomalous capacitance-voltage (C-V) degradation in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors (TFTs) under hot carrier stress. In vacuum hot carrier stress, both the gate-to-drain capacitance (CGD) and the gate-to-source capacitance (CGS) curves exhibited positive shifts due to electron trapping in the gate dielectric. In addition, an observed increase in capacitance value at a lower gate voltage in the CGDmeasurement only can be ascribed to interface state creation. However, when the hot carrier stress was performed in an oxygen-rich environment, the CGD-VGcurve showed a significantly positive shift due to the electric-field-induced oxygen adsorption near the drain terminal. The degradation in the CGS-VGcurve is due not only to the positive shift, but also the anomalous two step turn-on behavior. This phenomenon can be ascribed to the electron trapping in the gate dielectric and electric-field-induced oxygen adsorption on the channel layer, especially in the area adjacent to the drain terminal. The electron trapping increased the source energy barrier, with the electric-field-induced oxygen adsorption further raising the energy-band near the drain, resulting in a two-step turn-on behavior in the CGS-VGcurve.

We have investigated the gate bias stress-induced instability on the electrical properties with different pre-treatments for sol-gel derived amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs). The device with illuminating and heating pre-treatments under the positive/negative gate bias stress in vacuum had the smallest threshold voltage shift as the stress duration increased, while the device with oxygen gas pre-treatment exhibited an obvious variation. These electrical instabilities were ascribed to the charge trapping in the gate insulator and the oxygen/water adsorption on the active layer. It indicates that the specific pre-treatment for the a-IGZO film can improve the device stability. It also provides the important information for the subsequent passivation process concerning the pre-treatment of the active layer.

This work shows the effects of post-deposition annealing atmosphere and duration on the properties of sol-gel derived amorphous indium zinc oxide thin film transistors (a-IZO TFTs). Two different post-deposition annealing atmospheres, nitrogen and oxygen, were used in this study. Experimental results showed that the O2-annealed devices showed better electrical characteristics than the N2-annealed samples. Under O2-annealing, field effect mobility was enhanced to 1.47 cm2/V s, the threshold voltage increased to -4.61 V and the subthreshold swing improved to 0.86 V/dec. Also, the transfer characteristics of a-IZO TFTs improve with annealing time. X-ray photoelectron spectroscopy (XPS) analysis indicated that the chemical composition of the IZO film was modified by the oxygen annealing.

This paper investigates the environmental effects and related adsorbent species reactions on sol-gel derived amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs). The discrepancy between device characteristics measured in atmospheric and vacuum conditions was clarified through experiments with thermal annealing and different gas partial pressures. The measurement of a-IGZO TFTs in simulated water vapor environment was also utilized. We verified that the adsorbed water originating from the surrounding atmosphere can cause an increase in off-current and also enhance more oxygen molecule adsorption on the exposed back-channel surface, leading to more serious degradation in on-current.

The original influence of water on the back-channel of sol–gel derived amorphous indium–gallium–zinc-oxide thin film transistors was studied in various relative humidity environments. As humidity increased from 0 to 80%, the mobility increased from 0.22to0.24cm2∕(Vs), threshold voltage decreased from 6.6to4.4V, and subthreshold swing changed from 0.77to1.27V∕dec. The conflicting phenomenon among the three parameters was suggested to be due to a division of the gate voltage by the water molecules which adsorbed on the thin film transistor back-channel and acted as dipoles.

This article investigates the carrier transport phenomenon and multilevel switching mechanism of Cr2O3-based resistive random access memory (RRAM) with Pt∕Cr2O3∕TiNstructure. Before the forming process, the interfacial Schottky barrier dominates the carrier transport. The barrier heights of Pt∕Cr2O3and Cr2O3∕TiNare 0.7 and 0.96eV, respectively. After the forming process, RRAM at a low resistance state follows the Ohmic conduction. While RRAM is switched to a high resistance state during the reset process, the Frenkel-Poole emission becomes a dominant conduction mechanism. The multilevel resistance states were achieved by applying corresponding reset voltages to the device for controlling the trap levels of the Cr2O3layer.

This work investigates dynamic negative bias temperature instability (NBTI) in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with different rise and fall times. Experimental results reveal identical increases in the interface state density (Nit)induced by different dynamic NBTI stress conditions. Nevertheless, the degradation of the grain boundary trap (Ntrap)becomes more significant as rise time decreases to 1μs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrapincrease is assisted by this transient effect.

In this work, a mechanism of anomalous capacitance in p-channel low temperature polycrystalline silicon thin film transistors (LTPS TFTs) was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between the gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. By fitting the curve of the drain current vs electric field under off-state region, it was verified that the trap-assisted gate-induced drain leakage (TAGIDL) consists of the Pool–Frenkel emission and thermal field emission. In addition, the charge density calculated from the Cgsd-Vgmeasurement also has the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the TAGIDL. To suppress the anomalous capacitance, a band-to-band hot electron stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by TCAD software.

This article investigates the threshold voltage (Vt)shift induced by a self-heating effect for n-channel low temperature poly-Si thin film transistors (TFTs) and finds that there is a shift of more than 3 V in the negative direction after a self-heating operation of 100 ms. The negative Vtshift can be attributed to the charge-trapping effect caused by the holes generated by trap-assisted band-to-band thermionic field emission and trapped in the grain boundary of the poly-Si film substrate. We used lateral body contact structure to verify that this unusual Vtshift is related to the holes trapped in the substrate.

This work investigates negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin film transistors (LTPS TFTs) in a darkened and in an illuminated environment of different light intensities. Experimental results reveal that the generations of interface state density (Nit)are identical under various illuminated intensity NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap)under illumination was more significant than that for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrapdegradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region than from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase in Ntrapdegradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in the poly-Si bulk, affecting photosensitivity in LTPS TFTs.

In this work, the negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin-film transistors in a darkened and in an illuminated environment was investigated. Experimental results reveal that the generation of interface state density (Nit)showed no change between the different NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap)under illumination was more significant than that in the darkened environment. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress.

A technology to eliminate the photoleakage current of poly-Si thin-film transistors (TFTs) with top gate structure has been developed. A thin metal film is formed on the glass substrate to be used as a light-shielding layer. The light-shielding layer, buffer layer, and active island are patterned employing the same mask. The leakage current and the variation of subthreshold swing in the proposed devices are suppressed completely under illumination. Due to the parasitic capacitance in the overlap region between the drain side and the metal-shielding layer, a floating voltage coupled from drain bias influences the threshold voltage of the proposed poly-Si TFTs.

A tapered shape of Cu pattern by electrodeposition through mask is preferred for fabricating metal line on thin-film transistors (TFTs). The influence of individual organic additive [polyethylene glycol (PEG), bis-3-sodiumsulfopropyl disulfide (SPS)] on the sidewall shape of the Cu pattern was identified. A compromising effect shows up when both PEG and SPS are added owing to the competition of the behavior of two different organic additives during Cu electrodeposition. Therefore, a method has been developed for the fabrication of copper pattern used in TFTs, which forms a tapered pattern in one single Cu deposition step.