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Due to power consumption and speed limitations, the development of CMOS-based large-scale integrated circuits has stagnated in the post-Moore era. While superconducting digital integrated circuit is a promising solution due to its low power consumption and latency. However, the lack of large-scale cryogenic storage units prevents most superconducting chips from being deployed in practical applications. To fully utilize the advantages of superconducting chips and successfully apply them in processing large datasets, we propose a novel heterogeneous processor based on CMOS-based circuits and superconducting chips for processing pattern-matching tasks. In our proposed architecture, a novel communication architecture that enables high-speed, reliable communication between 12 GHz superconducting chips and CMOS circuits is proposed. The hardware overhead for high-speed communication in superconducting chips can be minimized by this approach. In addition, the data communication rate of a single channel can reach 12 Gbps. Simultaneously, we present a 12 GHz, large-scale superconducting chip with 6286 Josephson Junctions that can perform 16-bit pattern matching using the SIMIT-Nb03 process. We have successfully applied our proposed heterogeneous processor to the gene sequence alignment. The processor that uses only one superconducting chip has a throughput of 1.5 Gbp/s (billion base pairs per second), whereas a processor with two superconducting chips has 3 Gbp/s.

A hybrid computing system employing the superconductor central processing unit and semiconductor memory is a prospective strategy to boost speed and power performance. Aiming to convert coded signals at room temperature to single-flux-quantum (SFQ) logic signals in a cryogenic environment, this article presents two types of CMOS-to-SFQ interface circuits for return-to-zero (RZ) and nonreturn-to-zero (NRZ) coded signals transformation. One can double the data rate (DDR) of bipolar RZ signals, and the other can decode unipolar and polar NRZ signals. In the simulation using parameters of the SIMIT Nb03 process, both the interface circuits have up to 20 GHz sampling frequency, more than ±30% bias current margin, and tolerance toward 20 dB SNR white noise. The DDR interface circuit can generate SFQ pulses at both edges of 1.4–2.6 mA bipolar RZ signal, and the decoding interface circuit can interpret 0.2–0.6 mA unipolar and polar NRZ signal into SFQ pulses. The test circuits have been fabricated under the SIMIT Nb03 6 kA/cm2 process. In low-frequency measurement, the DDR interface circuit can convert 1.4–2.4 mA bipolar RZ signal, and the decoding interface circuit can convert 0.25–0.5 mA unipolar and polar NRZ signal with more than ±30% bias current margin. In high-frequency measurement, the DDR interface circuit shows an ability to convert a 3.33 GHz input signal.

Passive transmission line (PTL) has been widely applied in rapid single flux quantum (RSFQ) circuits, especially as the first choice of long-distance transmission in large-scale integrated circuits such as arithmetic and logic unit (ALU) and central processing unit (CPU). With the increasing demand of timing regulation, general bias margin is not enough to evaluate the performance of PTL circuits. Timing accuracy including propagation delay of the micro stripe line (MSL) and its delay skew is more critical for clock routine and signal transmission when employing PTL circuits. However, the related reports about the timing information of PTL circuits is limited in the single-value verification of the theoretical MSL's delay. More factors such as bias current, transmission length and system noise should be considered into the evaluation of the PTL circuits. This work focuses on the timing extraction of the designed PTL circuits through different control groups, and evaluates the timing discrepancy between the measurement and simulation. We adopt the method of time accumulation by increasing different lengths of MSL in the loop of the ring oscillator (RO) and subtract each other to evaluate the MSL's propagation delay. We analyzed MSLs of two layers (MSL1 and MSL2). The measured propagation delay of 1 ${\text{mm}}$ MSL is 8.20 ps/mm for MSL1 and 7.66 ps/mm for MSL2, which has a delay skew of 0.30 ${\text{ps}}$ and 0.57 ${\text{ps}}$ from the simulated value (8.23 ${\text{ps}}$). Within MSL transmission length of 5 ${\text{mm}}$, a maximum deviation of 1.2 ${\text{ps}}$ is adopted as time redundancy of PTL circuits applied in ALU and CPU design.

Along with the improvement of integration and the requirement of high-speed operation, the passive transmission line (PTL) plays a significant role in superconducting integrated circuits due to its intrinsic advantage of extremely low propagation delay and low signal loss in long-distance transmission. Good impedance matching is critical to reduce the signal reflection in the transmission line and maximize the power transferred. Based on the PTL wiring layer selection under SIMIT-Nb03 process, we studied the equivalent input/output impedance for Josephson junction (JJ) at the IO port and explored a method of impedance matching in rapid-single-flux-quantum circuits by adjusting the Stewart McCumber parameter ${\beta }_{\bm{C}}$ of the JJ in the design of the PTL's driver and receiver. Furthermore, the accompanying influence from JJ's modified ${\beta }_{\bm{C}}$ on the performance of the driver and receiver is evaluated to maximize the profit of the functional circuits. The common-used serial resistor is removed to obtain a balanced bias margin for the PTL circuits. The proposed PTL has been designed and tested based on SIMIT-Nb03 fabrication process. In total, $ \pm $30% bias margin for the PTL is achieved at low frequency and high frequency (40 GHz) contrast tests, including operation speed and transmission length as test vector. Additionally, a frequency sweep for 1 mm PTL is performed by the designed ring oscillator on the chip. The maximum working frequency is up to 129 GHz, with a margin duration of 8%.

We have been developing a power supply analysis tool for Josephson junction-based circuits, embedded in our analog simulator JSICsim, supporting power-related analysis functions such as current distribution, invalid DC biases, and variance map analysis. The power analysis procedure involves the power mesh layout processing based on different types of models. The power mesh is converted into a netlist, which will be used to form a top-level netlist together with the core netlist. Using JSICsim for simulation and iteration, the current distribution data could be obtained, and its static and dynamic heat map could be rendered for designers. In this article, we also demonstrate several testbench circuits fabricated by using SIMIT-Nb03 technology, providing their simulation and testing results with analysis. The results show that by using this power supply analysis tool, the designers can locate the potential high-risk areas in terms of the current distribution in their design and use this information for improvement before fabrication.

Model predictive current controller is a popular and effective technique to provide fast dynamic response in the field of motor control. However, conventional predictive controllers are susceptible to deteriorating control performance when model mismatch exists, such as changes in motor parameters due to the temperature variations. Therefore, this article proposes a precise model-aid extended state observer (MAESO) compensation-based real-time model predictive current controller with enhanced parameter robustness performance and high bandwidth. The predictive controller is converted into the form of multiparameter quadratic programming for online solution using numerical computational method and the constraints are linearized. In addition, the disturbances estimated by MAESO are fed back to the controller in the form of parameters for cycle-by-cycle compensation without extra controller design. Comparative simulations and experiments under different operating conditions are carried out to verify the effectiveness and superiority of the proposed method.

•Single-Flux-Quantum (SFQ) circuit has the advantage of ultra-high speed and low power consumption•A layout method called Maximum Operating Frequency Constraint (MOFC) is proposed for SFQ circuit•A 32-bit bit-parallel specialized processor is fabricated based on SIMIT-Nb03P process.•Our chip achieved an enerfy efficiency ratio of up to 251 GOPS/W.

Rapid single flux quantum (RSFQ) circuits have the advantages of high speed and low power consumption. The typical frequency of the RSFQ circuits is tens of GHz. Therefore, it is necessary to reliably test the high-frequency performance of RSFQ circuits simply and effectively. This paper proposes a new on-chip high-frequency testing method, which uses pseudo-random sequences generated by linear feedback shift register (LFSR) as the test vectors, and the output shift registers (SRs) to store the last piece of high-frequency testing result and read out it at low-frequency. Unlike the traditional high-frequency demonstration method of using the Input/Output SRs, our testing system can automatically generate a large number of test vectors to test the circuit at high frequency at low cost, making the whole high-frequency demonstration more reliable and convincing. On the other hand, this method is also a feasible and straightforward on-chip high-frequency test method for various RSFQ circuits. This work verified the proposed method, and the highest test frequency can reach 54 GHz while the circuit shows good operating margins.