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Silicon-on-insulator (SOI) technology offers many advantages for transistors while also presenting significant challenges in thermal management. The buried oxide (BOX) layer impedes vertical heat dissipation, rendering conventional cooling solutions based on air and liquid coolers inefficient. In this study, we propose a novel theoretical design of a holey silicon-based lateral thermoelectric cooler (TEC) that provides a unique cooling solution for SOI transistors. By redistributing heat laterally, this TEC overcomes the limitation of poor vertical heat dissipation caused by the BOX layer, meanwhile taking advantage of the sustained temperature gradient in the device layer. In addition, we present a novel precooling strategy which utilizes a long-time, optimal-voltage TEC cooling pulse to cool down a short-time, high-power-density heating pulse. We evaluate the cooling performance through simulation of two devices: an SOI transistor-TEC device and a $5\times5$ SOI transistor-TEC array device. Under a 10 $\mu \text{s}$ transient heat pulse with high-power density of 11000 W/cm2 (1.6 W), the SOI transistor-TEC device with a 10 $\mu \text{m}$ thick BOX layer can be cooled from 465.7 °C down to 407.4 °C ( $\Delta {T}$ = 58.3 °C) in peak hotspot temperature when precooled with a 1000 $\mu \text{s}$ TEC pulse, consuming 0.20 W of TEC power. Furthermore, the SOI transistor-TEC array device provides spatial temperature control by incorporating multiple coolers which enable selective cooling for individual transistor units without significant loss of cooling performance. In summary, our TEC design exhibits great potential in offering dynamic thermal management for a wide range of advanced SOI devices.