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This work investigates the abnormal phenomena that are observed in electrical characteristics under negative bias stress (NBS) in flexible p-channel low-temperature polycrystalline silicon thin-film transistors (p-channel LTPS TFTs) after TFTs being lifted off from a rigid substrate. During the lift-off process, mechanical strain accumulates in the buffer layer due to the unilateral force, thus resulting in the generation of defects in the buffer layer. Therefore, abnormal degradation behaviors in electrical characteristics of the lifted-off TFTs were observed during negative gate bias stress. A study on physical mechanisms is introduced to describe such abnormal phenomena, and it is confirmed that defects are produced in the buffer layer when the LTPS TFTs are lifted off. In addition, different device dimensions were discussed to support our proposed model. The findings in this work are supported by the discussion of electrical characteristics, trap state extraction, and COMSOL simulation.

In this work, the nonvolatile memory constructed on the tunnel thin-film transistors (tunnel-TFTs) using polycrystalline-silicon channel featuring ferroelectric HfZrOx layer is demonstrated for the first time. When the pulse voltages of program (PG) and erase (ER) are, respectively, 3.5 and −2 V with the pulsewidth of $1 ~\mu \text{s}$ , the threshold voltage modulation amount of the ferroelectric tunnel-TFT can reach −0.524 and 0.496 V, respectively. In addition, the endurance behaviors of the ferroelectric tunnel-TFT exhibit a strong PG/ER pulsewidth dependence. The wake-up effect of the ferroelectric layer becomes more pronounced as increasing the PG/ER pulsewidth. Moreover, the increase of the PG/ER pulsewidth also causes the ferroelectric tunnel-TFT to be subjected to the electrical dynamic stress effect, leading to the degradation of the subthreshold swing (SS) and the electron trapping effect. When the pulsewidth is 100 ns, the endurance is mainly dominated by the fatigue effect of the ferroelectric layer and the degradation of the SS. When the pulsewidth increases to $1 ~\mu \text{s}$ , the endurance is mainly dominated by the electron trapping effect of the ferroelectric layer in addition to the fatigue effect. The retention of the ferroelectric tunnel-TFT exhibits stable behavior at 50 °C. Consequently, the ferroelectric tunnel-TFT exhibits sufficient electrical performance and can be integrated with display panels and various sensor systems on smart wearable devices for edge computing applications.

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106cycles compared to SG mode’s 105cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRGand VERS.

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTHto meet circuit design requirements. Using a fixed positive VBGcan not only reduce the VTHof the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBGwill enhance the PGS degradation of TG. Consequently, the positive VBGis suggested to lower the VTHand improve the PGS of the device.

In this work, a ferroelectric tunnel thin-film transistor (FeT-TFT) with polycrystalline-silicon (poly-Si) channel and ferroelectric HfZrOxgate dielectric is demonstrated with analog memory characteristics for the application of synaptic devices. The FeT-TFT exhibits a much lower conduction current of ∼0.032 times in transfer characteristics and maximum conductance (Gd) of ∼ 0.14 to 0.2 times in potentiation and depression operation than the FeTFT due to FeT-TFT’s carrier transport mechanism: interband tunneling. This work employed pulse widths of 75, 150, and 300 ns to modulate Gd, and it was found that using a pulse width of 75 ns could achieve low asymmetry ∼ 1 and high Gdratio ∼ 20.63 under the consideration of operation speed. When the pulse time is increased, the potentiation and depression voltages can be significantly decreased to maintain the low asymmetry, but the Gdratio is also reduced. In addition, the endurance characteristic of poly-Si FeT-TFT is found to be strongly related to the degradation effect of subthreshold swing due to the dynamic stress effect in the endurance measurement. This result reveals that the reliability of ferroelectric devices is not only owing to the degradation of the remanent polarization.

Processes for fabricating a Ni nanocrystal (NC)-assisted low-temperature polycrystalline silicon thin film transistor (LTPS-TFT) nonvolatile memory device of noble stack below 600 \mbox{\circC} were successfully developed. The NCs were fabricated in H-plasma atmosphere by heating a nanosized Ni film to realize an appropriate nanoparticle distribution. Results show that NCs with a number density of ${\sim}5\times 10^{11}$ cm-2and a particle diameter of 4 to 12 nm can successfully be fabricated as charge-trapping centers for enhancing the device performance. The results also indicate that the data retentions at the initial time and after $10^{4}$ s for a SiO2/Ni-NCs/Si3N4/SiO2gate under the present stack of devices are about 2.2 and ${\sim}1.1$ V, respectively.