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State-of-the-art nanometric fabrication processes enable the integration of monolithic millimeter-wave (mm-wave) circuits. However, nanometric technologies are prone to process variations that may significantly impact the performance of the fabricated mm-wave circuits and dramatically reduce the fabrication yield. In order to improve the fabrication yield, extensive resources are required for tuning the functionality of each fabricated die in the production line, especially in the mm-wave domain. In this work, we implement and experimentally validate a machine learning-based calibration strategy for mm-wave circuits that significantly simplifies this tuning process. A machine learning algorithm is employed to predict the optimum values of a set of on-chip tuning knobs based on nonintrusive measurements provided by embedded process monitor circuits. The proposed technique is demonstrated on a 69-GHz power amplifier (PA) with one-shot calibration capabilities integrated in STMicroelectronics 55-nm CMOS technology. The experimental results on a set of 39 fabricated samples demonstrate the feasibility and performance of the proposed machine learning-based calibration for yield recovery and performance recentering applications.

Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques.

Abstract: Sigma–Delta (ΣΔ) modulators have made possible the design of high-resolution Analogue-to-Digital Converters (ADCs) with relaxed analogue circuitry precision by moving most of the design complexity to the digital domain. However, testing these ΣΔ ADCs is becoming a costly task due to trends towards high-resolution implementations and associated increase in samples required to extract key specifications. In this paper, we propose a Built-In Self-Test (BIST) technique for high-resolution ΣΔ ADCs. The technique, mostly digital, moves most of the test complexity to the digital domain, that is in-line with the philosophy of ΣΔ modulation. Both the test signal generation and the output response analysis are performed on-chip. The stimulus, a sinusoid encoded in a binary bit stream, is chosen to have very high quality in the bandwidth of the converter with the quantization error laying outside of the analogue modulator’s bandwidth. For the output response analysis, a sine-wave fitting algorithm is implemented on chip. For this, a digital sinusoidal stimulus of a very high precision is needed as a reference signal. In this paper, we generate this reference signal from the same input stimulus, by passing it through the digital filter already existing in the converter. Simulations results show the capability of this technique to obtain measurements of the SNDR (Signal-to-Noise-plus-Distortion Ratio) for a 16-bit audio ΣΔ ADC.

As semiconductor technologies evolve, the development of methodologies and tools for testing Integrated Circuits (ICs) become more complicated. With each new generation of devices, more and more transistors, in addition to other components such as resistors, capacitors, diodes and even Micro-Electro-Mechanical-Systems (MEMS), are integrated in a single chip. Generating and applying test stimuli for detecting device malfunction, and locating faults or design errors, becomes more and more difficult. Basic test aspects change with each new technology, such as failure mechanisms, fault models or the applicable test techniques. Test engineers struggle to keep pace with these changes that, in combination with ever increasing design complexity, make previous tools and methodologies unsuitable. In this paper, we will present a brief introduction to the field of IC testing and we will show how the incorporation on chip of transducer blocks modifies the design and test flow. Fundamental test concepts and techniques will be presented and illustrated for the case of testing embedded transducers.

With the rapid development of system-on-chip (SoC) applications, containing digital and analogue parts, the need for fast and reliable on-chip testing methods has become obvious. We present a method for a fast and accurate broadband determination of the behaviour of analogue and mixed-signal circuits. This technique is based on impulse response (IR) evaluation using pseudo-random Maximum-Length Sequences (MLS). This approach provides a large dynamic range and is thus an optimal solution for measurements in noisy environments and for low-power test signals. We will show the algorithms of the MLS generation and of the impulse response calculation which can be easily implemented on-chip.

A major task for the implementation of Built-In-Self-Test (BIST) strategies for MEMS is the generation of the test stimuli. These devices can work in different energy domains and are thus designed to sense signals which are generally not electrical. In this work, we describe, for different types of MEMS, how the required non-electrical test stimuli can be induced on-chip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The on-chip test signal generation is illustrated for the case of MEMS transducers which exploit such physical principles as time-varying electrostatic capacitance, piezo-resistivity effect and Seebeck effect. These principles are used in devices such as accelerometers, infrared imagers, pressure sensors or tactile sensors. For implementation, we have used two major MEMS technologies including CMOS-compatible bulk micromachining and surface micromachining. We illustrate the ability to generate on-chip test stimuli and to implement a self-test strategy for the case of a complete application. This corresponds to an infrared imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a suspended membrane that contains several thermopiles along the different support arms. The on-chip test signal generation proposed requires only slight modifications and allows a production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.

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