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Total-ionizing-dose (TID) effects are evaluated in back-gated indium–gallium–zinc oxide (IGZO) thin-film transistors irradiated under different gate biases. Negative-bias irradiation leads to worst-case degradation of TID response in these devices, primarily as a result of enhanced charge trapping in the SiO2 overlayer. The relatively small peak transconductance decrease after irradiation illustrates that IGZO transistors are much less sensitive to interface-trap buildup and other instabilities due to hydrogen release and transport than amorphous Si thin film transistors examined previously. The TID response of devices with different gate sizes is also investigated. No significant geometry dependence is observed, which is promising for future scaling down of the technology.

Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET and Gate All Around devices. We use Si4H10as Si precursor as it enables epitaxial Si growth at temperatures down to 330°C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.

With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

To cope with the devices requirements imposed with the ITRS roadmap, several technique are implemented to boost up the drive current. Two possible approaches are the introduction of SiGe channels and the use of Ge-based devices. This paper reviews the radiation hardness of both CMOS technologies, based on an experimental study of state-of-the-art devices, for potential use in space applications.

Germanium possesses higher electron and hole mobilities than silicon. There is a big leap, however, between these basic material parameters and implementation for high-performance microelectronics. Here we discuss some of the major issues for Ge metal oxide semiconductor field effect transistors (MOSFETs). Substrate options are overviewed. A dislocation reduction anneal 800°Cdecreases threading dislocation densities for Ge-on-Si wafers 10-fold to 107cm−2; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at ∼6monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for p+/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H2anneal for device performance is shown.