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In this article, we comprehensively investigate the potential of the digital polar radio transmitter architecture for multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) downlink system. In terms of throughput performance, we derive a lower bound for the average sum-rate achievable with Gaussian signaling inputs and zero-forcing (ZF) precoding based on Bussgang decomposition. By diagonal approximation, we derive an approximate, yet accurate, model for the distortion caused by uniform polar quantization, which can be used to evaluate the corresponding sum-rate in closed form. To assess the power efficiency, we provide power consumption models with realistic parameters and values for the quantized polar and Cartesian transmitters, based on state-of-the-art integrated circuit (IC) designs and measurements. Extensive numerical results demonstrate that the proposed quantized polar transmitter can enable excellent performance in terms of average sum-rate, symbol error rate (SER), and out-of-band (OOB) emission level, compared to the Cartesian architecture. Furthermore, the power consumption comparisons show that the digital polar transmitter can save more than 36% in the energy consumption under 64-antenna setting in typical 5G enhanced mobile broadband use cases, thus making it highly appealing for future power-efficient massive MIMO transmitter implementations.

The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

This article investigates the feasibility of combinerless multilevel outphasing transmitter as a potential architecture for large millimeter-wave (mmWave) phased arrays. We consider two distinct ways of distributing the component signals to the antennas and develop a model for the received signal at each radiated spatial direction from a phased array. Based on the received signal model, we derive expressions for the signal-to-distortion ratio as well as total power experienced at each spatial direction. Furthermore, antenna branch mismatches, overload distortion and quantization are considered, and an analytical model for the signal-to-distortion ratio at the intended receiver is derived. We additionally establish a model for comparing the achievable energy efficiency to those of the relevant reference methods. Extensive numerical experiments are carried out to verify the analytical works, and to assess the commonly used metrics of error vector magnitude (EVM) and total radiated power adjacent channel leakage ratio (TRP-ACLR). It is shown that the combinerless architecture is a valid option for mmWave phased arrays, demonstrating favorable EVM results and TRP-ACLR beyond the 28 dBc limit imposed by the 3GPP, even in the presence of the considered distortions. The conducted energy efficiency assessment shows that efficiency of the reference methods can be exceeded with sufficient amount of outphasing levels. The considered architecture is thus an interesting alternative for addressing the linearity vs. energy-efficiency challenge in mmWave phased-array systems.

This letter investigates the feasibility of the quantized digital polar transmitter architecture in a downlink multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) system, where a low amplitude resolution and a moderate phase resolution are utilized. We derive a lower bound on the average sum-rate achievable with Gaussian signaling inputs and linear precoding by a simple diagonal approximation for the quantization distortion. The analysis and simulations demonstrate that the quantized polar transmitter can enable excellent performance in terms of average sum-rate throughput, symbol error rate (SER), and out-of-band (OOB) emission level, thus providing an attractive option for the traditional Cartesian architecture.

RF-to-digital conversion is a recent approach to digital-intensive wireless receiver operation. Such converters often employ delta-sigma (ΔΣ) modulation to transcend the traditional divide between receiver RF front-ends and baseband analog-to-digital converters (ADC). Research on the direct delta-sigma receiver (DDSR) architecture is one example of the emergence of next-generation ΔΣ modulators. It embeds a direct conversion receiver front-end as part of a feedback-type ΔΣ modulator structure with an active loop filter, which extends ADC operation to RF and changes the role of the low-noise amplifier (LNA) and mixing stages. RF-to-digital converters thus merge the two formerly separate design domains, requiring a paradigm shift in both RF and ADC design methods. Accordingly, this paper uses the DDSR as an example to bridge the gap between RF and ADC design, by providing a systematic understanding of the role, modeling, and design strategy of the related complete RF front-end. Most importantly, the analysis produces new design equations that link analog RF stage properties to their continuous-time (CT) ΔΣ modulator coefficients, thus providing a useful circuit design tool.

Detecting the presence of primary users and ability to find white spaces in the spectrum are the key enablers of the opportunistic communication. This paper analyzes the trade-offs in cyclostationary-based spectrum sensing algorithm implementations in terms of performance, hardware complexity, and power consumption. The evaluation of the algorithm implementations is performed on field-programmable gate arrays. The analysis presented will provide the designer understanding of dependency between algorithm complexity and power consumption, which is inherently limiting factor of implementation feasibility for cognitive mobile devices.