Search

Several converters based on series-connected submodules have been reported in the literature for high voltage direct current (HVDC) applications. For these converters, the calculation of switching losses in the semiconductors is challenging since it is difficult to predict the instants of the switching actions. Analytical methods with low accuracy and methods based on detailed simulations with long computation time have been proposed in the literature for modular multilevel converters (MMC). In this context, this paper proposes a simulation-based method for calculation of losses on any converter topology based on stacks of half-bridge submodules balancing accuracy and computing time. The method is based on the time-domain simulation of a submodule stack model in Matlab/Simulink. Then, the converter key operation values obtained from the simulation, such as stack current and submodule control actions, are used to calculate the switching losses in a post-processing treatment. To validate the method, the submodule stack switching losses of a MMC and a DC-MMC are assessed. The method is compared against a detailed model simulation using PLECS platform as a reference and against analytical methods. Furthermore, a statistical analysis of the losses distribution among the submodules and a sensitivity analysis are performed. As result, the proposed method gives a good trade-off between accuracy and computing time. The contribution of this paper is the proposed method to assess switching losses in converters based on stacks of submodules, not only the MMC, with acceptable accuracy and low computing time, compared with other state-of-the-art methods.