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The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

Large-scale multibeam phased array systems suffer from interbeam interference (IBI) that should be canceled either in the analog or digital domain. In wideband systems such as fifth generation (5G), interference rejection over a wide bandwidth is challenging to achieve, not only due to nonidealities of the receiver chain but also due to the properties of the radio channel. This article presents a scalable IBI cancellation (IBIC) scheme at intermediate frequency (IF) using an IF receiver (IF-RX) chip. The IF-RX provides the flexibility of not just interference rejection between the subarrays but also wideband signal combining over multiple subarrays. It also provides wideband filtering before the analog-to-digital converter (ADC) to support 5G channel bandwidths of up to 800 MHz, high linearity, and low noise figure. A calibration method is proposed to find the cancellation coefficients for the IF-RX in measurements. Furthermore, a simplified over-the-air (OTA) IBIC model for analyzing rejection bandwidth limitations is presented. Interference rejection performance is demonstrated through the OTA measurements using 5G new radio (5G NR) signals. In the OTA measurements, 34–37-dB rejection was achieved for 50–100-MHz signals, while error vector magnitude (EVM) requirements of the 5G standards were met with good margins. Finally, the interference rejection over $4 \times 100$ MHz carrier aggregated 5G NR waveform was demonstrated.

This letter investigates the feasibility of the quantized digital polar transmitter architecture in a downlink multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) system, where a low amplitude resolution and a moderate phase resolution are utilized. We derive a lower bound on the average sum-rate achievable with Gaussian signaling inputs and linear precoding by a simple diagonal approximation for the quantization distortion. The analysis and simulations demonstrate that the quantized polar transmitter can enable excellent performance in terms of average sum-rate throughput, symbol error rate (SER), and out-of-band (OOB) emission level, thus providing an attractive option for the traditional Cartesian architecture.

RF-to-digital conversion is a recent approach to digital-intensive wireless receiver operation. Such converters often employ delta-sigma (ΔΣ) modulation to transcend the traditional divide between receiver RF front-ends and baseband analog-to-digital converters (ADC). Research on the direct delta-sigma receiver (DDSR) architecture is one example of the emergence of next-generation ΔΣ modulators. It embeds a direct conversion receiver front-end as part of a feedback-type ΔΣ modulator structure with an active loop filter, which extends ADC operation to RF and changes the role of the low-noise amplifier (LNA) and mixing stages. RF-to-digital converters thus merge the two formerly separate design domains, requiring a paradigm shift in both RF and ADC design methods. Accordingly, this paper uses the DDSR as an example to bridge the gap between RF and ADC design, by providing a systematic understanding of the role, modeling, and design strategy of the related complete RF front-end. Most importantly, the analysis produces new design equations that link analog RF stage properties to their continuous-time (CT) ΔΣ modulator coefficients, thus providing a useful circuit design tool.

A prototype design of upconverter and downconverter units for a double-conversion cable-modem RF tuner are presented. The upconverter upconverts a channel from 47–862 MHz input band to around 1575 MHz intermediate frequency. The image-reject downconverter shifts the channel to 36.125 MHz (EU) or to 43.75 MHz (US). The upconverter includes a variable-gain low-noise amplifier, a double-balanced mixer, a three-stage VCO bank for LO generation and a divide-by-two circuit for driving an external PLL. The downconverter includes a LNA, image-reject mixers in Hartley configuration, a 3-stage polyphase filter, an IF-amplifier and a SAW driver. For the second LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and a divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for the selection of LSB/USB injection. All building blocks are presented in this paper and experimental results are given from the upconverter, downconverter, and RF tuner demonstrator including SAW filters with center frequencies at 1575 and 44 MHz. The circuits are fabricated in a 0.9-μ m SiGe bipolar process.A prototype design of upconverter and downconverter units for a double-conversion cable-modem RF tuner are presented. The upconverter upconverts a channel from 47–862 MHz input band to around 1575 MHz intermediate frequency. The image-reject downconverter shifts the channel to 36.125 MHz (EU) or to 43.75 MHz (US). The upconverter includes a variable-gain low-noise amplifier, a double-balanced mixer, a three-stage VCO bank for LO generation and a divide-by-two circuit for driving an external PLL. The downconverter includes a LNA, image-reject mixers in Hartley configuration, a 3-stage polyphase filter, an IF-amplifier and a SAW driver. For the second LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and a divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for the selection of LSB/USB injection. All building blocks are presented in this paper and experimental results are given from the upconverter, downconverter, and RF tuner demonstrator including SAW filters with center frequencies at 1575 and 44 MHz. The circuits are fabricated in a 0.9-μ m SiGe bipolar process.

Most radio frequency voltage-controlled harmonic oscillators are tunedby changing the capacitance of a pn-junction diode. The inadequate capacitancetuning range of the pn-junction diode severely limits the achievable frequencytuning range of the oscillator. Two methods for extending the tuning range of monolithic LC-oscillators are discussed in this paper. The first approach is touse actively synthesized capacitor based on the Miller effect instead of a pn-junction varactor diode for the VCO tuning. An analytical model is developed forstudying the capacitance tuning range and the corresponding Q-value. Inthe second approach we are using a balanced variable impedance converter for theVCO tuning. In this approach tuning is based on current steering using the Gilbertcell. Altogether nine experimental circuits have been fabricated with a 0.8 μmBiCMOS process. All circuits oscillate around 2 GHz and tuning ranges exceeding30% have been measured.

Three LNAs at 2 GHz frequency range have been implemented in a SiGe Bipolar process targeted for a universal mobile telecommunications system. The LNAs are operating in two gain modes and they include a power-down mode. Both on-wafer and packaged LNAs were measured. Noise figure below 2 dB with IIP3 of 1 dBm and gain exceeding 15 dB has been achieved. LNAs work from a 2.7–5.5 V power supply. A figure of merit method is used to compare this work to other published LNAs.