Search

The paper describes wafer-scale memory design with network logic based on switching register circuit (SW-REG), and defect tolerance schemes. Such a wafer-scale memory is an array of chips, each consisting of a memory core and SW-REG. The SW-REG links neighboring chips of the same column, and each column is independently accessible from the outside. Monte Carlo simulation demonstrated that addition of driver transistors and spare lines to common signals, and bypass lines to SW-REG are optimum defect tolerance schemes. When using 64 Mbit DRAM memory core on an 8-inch wafer, wafer-scale memory gives higher memory capacity than corresponding discrete chip system; for 5 percent memory core yield, 13 times higher memory capacity is achieved. [ABSTRACT FROM AUTHOR]

This paper proposes hierarchical redundancy configurations for defect tolerance of large-area monolithic LSIs (wafer-scale integrated circuits or WSIs) with array structures. It also specifies how much the integration scales can be increased by expanding hierarchical levels, based on four kinds of one-dimensional/two-dimensional array-connection models. Hierarchical redundancy helps to extend the defect tolerance coverage to additional replacement circuits while maintaining a high level of spare effectiveness. An estimate base on the evaluation of nonredundant additional replacement-circuit scales indicates that four-level hierarchical redundancy configurations can increase integration scales by a factor of 64 to 1024 compared to nonredundant LSIs. [ABSTRACT FROM AUTHOR]

Hierarchical redundancy using defect-tolerant replacement circuits is proposed as a means to increase the yield of large-area LSIs (WSIs) with mesh-connected array structures. The defect-tolerant replacement circuits can be constructed by using direct-connection paths and distributed switches in basic k-out-of-n redundancy schemes. When the proposed redundancy configurations are applied to two-dimensional orthogonal-array WSIs, they reduce the number of switches not covered by any spare replacements. An estimate of defect tolerance indicates that the proposed redundancy configurations can increase the integration scale of under l-μm CMOS design circuits to about 400 times that of general nonredundant LSIs. [ABSTRACT FROM AUTHOR]