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With modern integrated circuits (ICs) operating at the gigahertz range of operation, the single-event (SE) cross section of an average logic circuit feeding data into a conventional latch has become comparable to the latch SE cross section. Logic SE cross sections at advanced FinFET technology nodes are analyzed to identify the “Threshold Frequencies” at which the logic SE cross section for a typical logic circuit exceeds that of the latch following it. The Threshold Frequency as a function of particle linear energy transfer, supply voltage, and latch design are analyzed for the 16-, 7-, and 5-nm bulk FinFET technology nodes. Results show that the Threshold Frequency is of the order of hundreds of megahertz at these nodes for all test conditions used in this study. Understanding the Threshold Frequency concept and trends will allow designers to harden circuits efficiently to meet design specifications with a minimum performance penalty.

Single-port (SP) and two-port (TP) static random access memory (SRAM) arrays in a commercial 5-nm FinFET technology were exposed to alpha particles at ambient and elevated temperatures up to 100 °C. Results show that increasing operating temperatures of these devices leads to significant changes in single-event upset (SEU) cross sections and multicell upset rates. Technology computer-aided design (TCAD) simulations are used to investigate the changes in charge collection and its relationship with changes in restoring current to affect storage node susceptibility. Simulations show that diffusion charge collection increases significantly for low LET particles incident outside drain regions of storage nodes. However, increasing drive current with temperature for FinFET transistors leads to decreasing SEU cross section for temperatures rising from 25 °C to 75 °C. Differences in charge collection and capacitance between SP and TP cell designs lead to decreasing SEU cross section for SP cells and increasing cross section for TP cells as temperature increases to 100 °C. These changes in vulnerability may lead to inaccurate predictions from accelerated testing at ambient temperatures if real operational temperatures are different.

Rapid advancements in semiconductor technologies have enabled circuit operation at gigahertz (GHz) frequencies. However, conventional radiation hardening by design (RHBD) methods may encounter challenges in the GHz frequency domain, leading to increased single-event upset (SEU) rates. In this study, the SEU susceptibility of flip-flop (FF) designs in a 5-nm bulk FinFET technology node, both with and without hardening techniques, operating at frequencies up to 0.7 GHz are assessed. Comprehensive experiments involving heavy-ion and alpha particles were conducted across a wide range of supply voltages and frequencies to investigate the SEU cross sections. Results demonstrate the relationship between SEU cross section, operating frequency, and particle linear energy transfer (LET) values for FF designs employing temporal and spatial hardening techniques. Notably, all hardened designs examined in this work exhibit significantly higher SEU cross sections when operating at 0.7 GHz compared to 2.5 MHz, approaching or surpassing the SEU cross section of an unhardened conventional D-FF. These findings underscore the significance of considering high-frequency and dynamic operational data, as relying solely on static or low-frequency information can lead to a substantial underestimation of SEU cross sections, thereby elevating failure rates in deployed electronic systems.

Embedded Silicon Germanium (eSiGe) is used in the channel region of PFET devices at the 22-nm FD SOI node. The use of eSiGe results in channel regions becoming strained, which results in better hole mobility and increased performance. However, if the active diffusion regions are too short on each side of a PFET gate, then the effect of channel strain is reduced, and performance is reduced. The Continuous Active Diffusion (CnRx) layout construct suggested by the foundry is a way to help keep channel strain present within a single-cell design. In this article, the CnRx construct is implemented in a 22-nm FD SOI test chip and soft error rates (SER) of stacked-transistor flip-flops (FFs) are shown to increase with heavy ion irradiation. The effect of channel strain on PFETs results in higher collected charges from ion strikes, and charges are more easily passed between adjacent transistors through strained channels. However, with careful schematic and layout design, these effects can be mitigated to produce both high-performance and radiation-tolerant cells using the CnRx construct.

Because of the isolation of transistors, fully depleted silicon-on-insulator (FDSOI) technology nodes have shown better single-event upset (SEU) resilience compared with bulk technology nodes. Additional radiation-hardening-by-design (RHBD) techniques can further improve the SEU performance. In this article, the SEU performance of multiple RHBD flip-flop (FF) designs using the guard-gate (GG) circuit at a 22-nm FDSOI technology is presented, including a conventional FF, a GG FF, a dual-feedback-recovery (DFR) FF, and a GG-dual-interconnected storage cell (DICE) FF. Irradiation results showed significant reductions in SEU cross sections for hardened designs compared to the conventional design. Specifically, the conventional GG design demonstrates more than $100\times $ improvement over a conventional FF design, while DFR and GG-DICE designs showed no upsets for all test conditions. Further analysis was carried out to explain the SEU performance differences between the GG and DFR FF designs, and it is noted that proper layout arrangement is critical for achieving ideal SEU mitigation in this FDSOI technology node.

Fully-depleted silicon-on-insulator (FDSOI) technology nodes offer better single-event (SE) performance compared with comparable bulk technologies. However, upsets are still possible at nanoscale feature sizes and additional hardening techniques need to be explored. This article presents the single-event upset (SEU) performance of multiple flip-flop (FF) designs using the stacked-transistor hardening technique at a 22-nm FDSOI technology node. Irradiation results show significant reductions in SEU cross sections for stacked-transistor-based hardened designs compared to a conventional design. Alpha particle exposures showed zero upsets for all D-flip-flop (DFF) designs tested. When exposed to heavy-ions, the stacked-transistor DFF design showed a $17\times $ improvement over a conventional DFF design at an LET value of 47 MeV-cm2/mg. The stacked-transistor design with the charge-canceling technique showed upsets when particle LET exceeded 93.8 MeV-cm2/mg and at a high angle of incidence. The stacked-transistor design with the interleaving technique showed zero upsets for all test conditions.

Light scattering from VO2microrods (MRs) synthesized on a silicon substrate is studied as a function of temperature and wavelength through the insulator‐to‐metal (IMT) and the metal‐to‐insulator (MIT) transitions. Light scattering exhibits substantial and reproducible changes. By focusing the light on individual MRs, it is shown that for small‐sized MRs (<1 × 10 μm), the IMT and MIT are very sharp with transition temperatures varying within 31–64 °C (IMT) and within 58–76 °C (MIT). In contrast, for large‐sized MRs (≈4 × 40 μm), only the IMT at 68 °C is sharp, whereas MIT is stretched with a prominent low‐temperature shoulder at 35–50 °C. The observed phenomena are assumed to be connected with the external substrate‐induced mechanical stress emerging during the phase transition. A simple model is developed to explain both the temperature‐stretched MIT and the low‐temperature shoulder. Light scattering from VO2microrods exhibits considerable changes through the insulator‐metal (IMT) and metal‐insulator (MIT) phase transitions. Measurements show that the IMT occurs at 68 °C, whereas the MIT stretches between 31 and 64 °C. A simple model relates the stretching of the MIT to the external substrate‐induced mechanical stress that emerges during the IMT.

A new approach of lithium electrochemical (de)intercalation material has been put forward. This approach requires a two-compound (physically or chemically) composite in which one is a chemically and electrochemically stable and porous (tunnel, cage, layer, etc.) compound such as clay or zeolite, and the other is a chemically and electrochemically stable and metallic compound such as graphite, metal powder or black carbon. Neither does the redox couple in this composite absolutely exist nor does the redox reaction, which is associated with electrochemical charge and discharge processes when this composite is used as an cathodic electrode in a lithium battery cell. In this paper, we show the results of the lithium electrochemical intercalation process in both black carbon-mixed zeolite and clay electrodes. In these solid electrodes, black carbon serves to delocalize (transport) electrons for balancing the charges while zeolite and clay offer the neutrally reversible sites for lithium ions. This approach can hopefully become a guide for the designing of new intercalation material and so will be very important in the application of the lithium rechargeable battery.

A new phenomenon of Li electrochemical (de)intercalation on the pure mineral clay materials has been evidenced for the first time. These tests are initialized by the idea of putting an electronic conducting polymer or a multi-valent metal oxide in the layer of the clay to modify the electronic properties and also to modulate the charge and discharge potential of the clay during the Lithium electrochemical (de)intercalation processing. In this paper, as the beginning of our research, we will first show the results of Lithium electrochemical charge and discharge processes on pure clay materials.