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Auger analysis has been used to detect thin SiO2 layers at the interface of the ITO/Si solar cell. The energy shift and line‐shape changes of the Si LVV line were used to determine the chemical bonding state of the interfacial Si. An exact determination of the SiO2 thickness was not possible, but it is estimated that the SiO2 layer of the best cell is in the range 12–20 A˚. The interfacial SiO2 layers of cells fabricated at 373 °C appear thicker and more completely developed than that of cells fabricated at room temperature.

The results of a successful demonstration of the selection module of an optoelectronic parallel-processing database filter is presented. The module utilizes 4 × 4 arrays of and and xor logic gates that respectively perform the functions of reducing the data fields and determining a match between the input data and a selection argument. The logic arrays were fabricated with InGaP/GaAs heterojunction phototransistors that drive vertical-cavity surface-emitting lasers (VCSEL’s). The VCSEL’s provide the free-space optical interconnection between stages. The design of the system and the optical power budget are discussed.

A number of nonnumerical processing applications, including database management, full text search, and pattern recognition rely heavily on digital comparisons. The development of massive-capacity optical memories coupled with the high speed and parallelism of optics have led to the investigation of optical techniques for nonnumerical processing. This paper proposes a system design for an optical comparator capable of performing multiple equal-to, less-than, and greater-than comparisons between pairs of binary words. The comparator consists of three two-dimensional arrays of optical elements based on a new optical logic device called the light-amplifying optical switch. The first two stages contain inverters, nor gates, and flip-flops, while the third stage is a custom-designed winner-takes-all network. With a compact design and with small high-speed devices a comparator with 2.5 × 10^4 pixels could theoretically attain a processing rate of approximately 4 × 10^10 16-bit word comparisons/s.

An optoelectronic bitonic sorter based on a recirculating architecture is presented. The data are input in word parallel-bit parallel fashion and processed by two smart pixel arrays made up of bitwise compare-and-exchange modules. Along with the logic design, the control and synchronization of the bitwise compare-and-exchange modules are discussed. Finally, the capacity, hardware requirements, response time, and throughput of the recirculating bitonic sorter are compared with a pipeline implementation. The proposed recirculating architecture is shown to require less hardware than the pipelined systems. However, the decrease in hardware results in a decrease in system throughput.