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Wireless sensor networks (WSNs) provide a promising approach to monitor the physical environments, to prolong the network lifetime by exploiting the mutual correlation among sensor readings has become a research focus. In this paper, we design a hierarchical network framework which guarantees layered-compression. Meanwhile, a data sorting-based adaptive spatial compression scheme (DS-ASCS) is proposed to explore the spatial correlation among signals. The proposed scheme reduces the amount of data transmissions and alleviates the network congestion. It also obtains high compression performance by sorting original sensor readings and selectively discarding the small coefficients in transformed matrix. Moreover, the compression ratio of this scheme varies according to the correlation among signals and the value of adaptive threshold, so the proposed scheme is adaptive to various deploying environments. Finally, the simulation results show that the energy of sorted data is more concentrated than the unsorted data, and the proposed scheme achieves higher reconstruction precision and compression ratio as compared with other spatial compression schemes. [ABSTRACT FROM AUTHOR]

The primary goal of the presented experiment was to judge the usefulness of FPGA technology in the sorting operation performed by computer systems. We were interested to see if it was possible to achieve better system performance and lower energy consumption when the CPU is supported by FPGA chips. The method of custom processing was applied. We proposed dedicated sorting hardware to increase performance and save energy. Our concept addresses High Throughput Computing (HTC) systems. The custom hardware approach was proposed because this technique is available in supercomputing infrastructures today. Another important issue of the work is that the hardware was programmed using High Level Language (HLL). As a semiconductor platform for hardware implementation the FPGA was chosen. We evaluated the efficiency of an FPGA based sorting processor that was programmed in Mitrion-C HLL. The FPGA approach was compared to the CPU approach in terms of efficiency and power consumption. [ABSTRACT FROM AUTHOR]