1. A neural net architecture for hardware implementation of a temporal pattern discrimination model.
- Author
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Takahashi, Sei and Sekine, Yoshifumi
- Subjects
ARTIFICIAL neural networks ,COMPUTER network architectures ,COMPUTER storage devices ,LOGIC circuits ,COMPUTER peripherals ,COMPUTER input-output equipment - Abstract
This paper proposes a neural net architecture for hardware implementation of a temporal pattern discrimination model. The elements constituting the hardware have the characteristics of delays, thresholds, and refractoriness that are useful for implementing a model in hardware. First, it shows that a temporal pattern short-term memory structure, similar to TDNN, can be implemented by connecting the hardware elements only serially. Next, it constructs a neocognitron-type temporal data recognition model (Neo-TDRM) using this short-term memory structure by using a neocognitron that is robust with respect to pattern positional lags or shape changes as a discrimination model. Results of computer simulation of single-channel mouse brain wave discrimination experiments show that the system can correctly discriminate even waveforms that are extended or contracted temporally or spatially. In addition, the proposed model is shown to be suitable for hardware implementation compared with the neocognitron constructed for similar discrimination experiments from the point of view of the number of cells or the number of wires required, since the number of cells of the Neo-TDRM can be reduced to about 1/4 and the number of wires to about 1/18. © 2004 Wiley Periodicals, Inc. Syst Comp Jpn, 35(9): 104–112, 2004; Published online in Wiley InterScience (
www.interscience.wiley.com ). DOI 10.1002/scj.20075 [ABSTRACT FROM AUTHOR]- Published
- 2004
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