23 results on '"Chang, S. Z."'
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2. 4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration
3. A > 64 Multiple States and > 210 TOPS/W High Efficient Computing by Monolithic Si/CAAC-IGZO + Super-Lattice ZrO2/Al2 O3/ZrO2 for Ultra-Low Power Edge AI Application
4. Development of Highly Manufacturable, Reliable, and Energy-Efficient Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM)
5. Performance Evaluation of 3D Memory-Logic Hybrid Bond Stacking by RLC Delay Model for Edge Computing Applications
6. Novel Analog in-Memory Compute with > 1 nA Current/Cell and 143.9 TOPS/W Enabled by Monolithic Normally-off Zn-rich CAAC-IGZO FET-on-Si CMOS Technology
7. Transistor threshold voltage modulation by Dy2O3 rare-earth oxide capping: The role of bulk dielectrics charge
8. Understanding and prediction of EWF modulation induced by various dopants in the gate stack for a gate-first integration scheme
9. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
10. Low VT metal-gate/high-k nMOSFETs — PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions
11. Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $\hbox{La}_{2}\hbox{O}_{3}/\hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High-$\kappa$ Dielectrics and Si Channel
12. Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)
13. Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $\hbox{Dy}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics
14. Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer
15. Demonstration of Metal-Gated Low $V_{t}$ n-MOSFETs Using a Poly-$\hbox{Si/TaN/Dy}_{2}\hbox{O}_{3}/\hbox{SiON}$Gate Stack With a Scaled EOT Value
16. Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window
17. Nitrogen Profile and Dielectric Cap Layer (Al2O3, Dy2O3, La2O3) Engineering on Hf-Silicate
18. Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack
19. Cyclotron-resonance studies in relaxedInxGa1−xAs (0≤x≤1) epilayers
20. Photoluminescence study of highly mismatched In0.53Ga0.47As epilayers grown on InP-coated GaAs substrates
21. Raman-line-shape study ofInxGa1−xAs on InP and GaAs substrates
22. Two‐dimensional electron gases in delta‐doped GaAs/In0.25Ga0.75As/GaAs heterostructures
23. The δ-Doped In0.25Ga0.75As/GaAs Pseudomorphic High Electron Mobility Transistor Structures Prepared by Low-Pressure Metal Organic Chemical Vapor Deposition*
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