78 results on '"Haendler, S."'
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2. Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology
3. Intrinsic ESD robustness on new high voltage N/PMOS devices in 28 nm FDSOI UTBB CMOS technology through TLP/VFTLP characterizations
4. Impact of Gamma irradiation on advanced Si/SiGe:C BiCMOS technology: comparison versus X-ray
5. Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing
6. 28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications
7. 28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications
8. Effects of Total Ionizing Dose on 1-V and Low Frequency Noise characteristics in advanced Si/SiGe:C Heterojunction Bipolar Transistors
9. Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K
10. Reliability assessment of 4GSP/s interleaved SAR ADC
11. Characterization, modeling and comparison of 1/f noise in Si/SiGe:C HBTs issued from three advanced BiCMOS technologies
12. Enhanced design performance thanks to adaptative body biasing technique in FDSOI technolologies
13. Low Frequency Noise in advanced 55nm BiCMOS SiGeC Heterojunction Bipolar Transistors: Impact of collector doping
14. Drain current local variability from linear to saturation region in 28nm bulk NMOSFETs
15. 28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications
16. Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin box SOI MOSFETs suitable for circuit simulators
17. Characterization and modeling of drain current local variability in 28 and 14 nm FDSOI nMOSFETs
18. Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature
19. Drain current local variability from linear to saturation region in 28nm bulk NMOSFETs
20. Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction
21. Low frequency noise temperature measurements in SiGe:C heterojunction bipolar transistors
22. Hot carrier degradation mechanisms of short-channel FDSOI n-MOSFETs
23. Measurement and characterization of low frequency noise collector current in 0.13 μm SiGe:C HBTs
24. Full front and back gate voltage range method for the parameter extraction of advanced FDSOI CMOS devices
25. Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs
26. Low frequency noise statistical characterization of 14nm FDSOI technology node
27. A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives
28. Study of low frequency noise in advanced SiGe:C heterojunction bipolar transistors
29. Dispersion study of DC and Low Frequency Noise in SiGe:C Heterojunction Bipolar Transistors used for mm-Wave to Terahertz applications
30. Impact of low‐frequency noise variability on statistical parameter extraction in ultra‐scaled CMOS devices
31. Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs
32. Characterization and modeling of low frequency noise in 0.13 µm BiCMOS SiGe:C heterojunction bipolar trasnsistors
33. The impact of high Vth drifts tail and real workloads on SRAM reliability
34. Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5μm down to 20nm
35. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
36. Impact of dynamic variability on the operation of CMOS inverter
37. Unexpected impact of germanium content in SiGe bulk PMOSFETs
38. Low frequency noise measurements of advanced BiCMOS SiGeC Heterojunction Bipolar Transistors used for mm-Wave to terahertz applications
39. Evolution of low frequency noise and noise variability through CMOS bulk technology nodes
40. Characterization and modeling of low frequency noise in CMOS inverters
41. Switching energy efficiency optimization for advanced CPU thanks to UTBB technology
42. Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs
43. Characterization and Modeling of Back Bias Impacts on Remote-Coulomb-Limited Mobility in UTBB-FDSOI Devices
44. Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs
45. Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates
46. 28nm FDSOI technology platform for high-speed low-voltage digital applications
47. Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology
48. Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances
49. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
50. Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors
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