61 results on '"Kosuge, Atsutake"'
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2. Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS
3. Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application
4. A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
5. A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
6. A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS
7. A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network
8. 1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 μm CMOS
9. A183.4-nJ/Inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique
10. A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA
11. A 12.8-Gb/s 0.5-pJ/b Encoding-less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET
12. A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion
13. Wireless Interconnect in Electronic Systems
14. Connectivity in Electronic Packaging
15. A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
16. Proximity Wireless Communication Technologies: An Overview and Design Guidelines
17. A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic
18. A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias
19. 3D-Stacked SRAM Using Near-Field Wireless Communication
20. A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
21. A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
22. An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique
23. Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format
24. A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
25. A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
26. A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna
27. A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation
28. A 7-nm FinFET 1.2-TB/s/mm$^{2}$ 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
29. A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-μm CMOS
30. Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface
31. mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications
32. A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network
33. A Physical Verification Methodology for 3D-ICs Using Inductive Coupling
34. A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net
35. A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna
36. A bonding-less 5-GHz RFID module using a 300um x 500um IC chip
37. An SoC-FPGA-Based Iterative-Closest-Point Accelerator Enabling Faster Picking Robots
38. POISON: Human Pose Estimation in Insufficient Lighting Conditions Using Sensor Fusion
39. A 1200×1200 8-Edges/Vertex FPGA-Based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation Systems
40. An RGB/Infra-Red camera fusion approach for Multi-Person Pose Estimation in low light environments
41. An Object-Pose Estimation Acceleration Technique for Picking Robot Applications by Using Graph-Reusing k-NN Search
42. A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications
43. A 6Gb/s rotatable non-contact connector with high-speed/I2C/CAN/SPI interface bridge IC
44. A 6Gb/s rotatable non-contact connector with high-speed/I2C/CAN/SPI interface bridge IC
45. Basic study of non-contact connector for high-speed space cable transmission: Space fibre, short paper
46. A 1 Tb/s/mm2 inductive-coupling side-by-side chip link
47. A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver
48. A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver
49. Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO
50. Analytical thruchip inductive coupling channel design optimization
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