69 results on '"Mak, Wai-Kei"'
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2. Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group Movement
3. Efficient Qubit Routing Using a Dynamically-Extract-and-Route Framework
4. Hybrid-Row-Height Design Placement Legalization Considering Cell Variants
5. Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization
6. Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem
7. Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement
8. HybridGP: Global Placement for Hybrid-Row-Height Designs*
9. Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization
10. A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits with Maximum Path Length Consideration
11. A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
12. Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs
13. Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os
14. Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement
15. A practical detailed placement algorithm under multi-cell spacing constraints
16. Pin Assignment Optimization for Multi-2.5D FPGA-based Systems
17. Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration
18. Making split fabrication synergistically secure and manufacturable
19. Making split fabrication synergistically secure and manufacturable
20. Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment
21. Minimum Implant Area-Aware Placement and Threshold Voltage Refinement
22. A routing framework for technology migration with bump encroachment
23. Mixed-Cell-Height Standard Cell Placement Legalization
24. Pin Accessibility-Driven Detailed Placement Refinement
25. Optimizing DSA-MP decomposition and redundant via insertion with dummy vias
26. Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration
27. Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs
28. Minimum implant area-aware placement and threshold voltage refinement
29. Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations
30. Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography
31. Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography
32. Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout
33. Double patterning-aware detailed routing with mask usage balancing
34. A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules
35. Flexible packed stencil design with multiple shaping apertures for e-beam lithography
36. Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design
37. MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules
38. Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement
39. Rethinking the Wirelength Benefit of 3-D Integration
40. Power-Driven Flip-Flop Merging and Relocation
41. Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign
42. SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement
43. Power-driven flip-flop merging and relocation
44. FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
45. Cut-demand based routing resource allocation and consolidation for routability enhancement
46. Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design
47. FOARS
48. SafeChoice
49. Ginkgolides and bilobalide selectively regulate the expression of nitric oxide synthases
50. An institutional perspective of the China-based companies in Hong Kong
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