213 results on '"Malik, Sharad"'
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2. Chapter 4. Conflict-Driven Clause Learning SAT Solvers
3. Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking
4. SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications
5. Synthesizing Environment Invariants for Modular Hardware Verification
6. INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms
7. ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions
8. Post-Silicon Fault Localization with Satisfiability Solvers
9. Propositional SAT Solving
10. Lazy Self-composition for Security Verification
11. CNNFlow: Memory-Driven Data Flow Optimization for Convolutional Neural Networks
12. Compositional Verification Using a Formal Component and Interface Specification
13. Usage-Based RTL Subsetting for Hardware Accelerators
14. Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions
15. IC3 - Flipping the E in ICE
16. Trace-based Analysis of Memory Corruption Malware Attacks
17. Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators
18. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
19. Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables
20. Fast Interpolating BMC
21. Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom
22. Reduction of Resolution Refutations and Interpolants via Subsumption
23. Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses
24. Leveraging Processor Modeling and Verification for General Hardware Modules
25. Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation
26. SAT Based Verification of Network Data Planes
27. Model Checking Unbounded Concurrent Lists
28. Modeling Firmware as Service Functions and Its Application to Test Generation
29. Runtime Verification: A Computer Architecture Perspective
30. Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search
31. passert: A Tool for Debugging Parallel Programs
32. Verification of Computer Switching Networks: An Overview
33. Parallel Assertions for Architectures with Weak Memory Models
34. Wolverine: Battling Bugs with Interpolants
35. Parameterized Model Checking of Fine Grained Concurrency
36. Boolean Satisfiability
37. MADL—An ADL Based on a Formal and Flexible Concurrency Model
38. MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications
39. Architecture Description Languages for Retargetable Compilation
40. A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors
41. A Case for Runtime Validation of Hardware
42. On Solving the Partial MAX-SAT Problem
43. Solving Quantified Boolean Formulas with Circuit Observability Don’t Cares
44. Lemma Learning in SMT on Linear Constraints
45. Symmetry Reduction in SAT-Based Model Checking
46. Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems
47. Zchaff2004: An Efficient SAT Solver
48. Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms
49. Power Analysis of Embedded Software: First Step Towards Software Power Minimization
50. Architecture Description Languages for Retargetable Compilation
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